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Volume 43, Numbers 5/6, 1999
IBM S/390 Server G5/G6 |
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Table of contents: HTML PDF ASCII |
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This article: HTML PDF ASCII |
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Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors - References
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by
R. M. Averill III, K. G. Barkley, M. A. Bowen, P. J. Camporese, A. H. Dansky, R. F. Hatch, D. E. Hoffman, M. D. Mayo, S. A. McCabe, T. G. McNamara, T. J. McPherson, G. A. Northrop, L. Sigal, H. H. Smith, D. A. Webber, P. M. Williams |
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References
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C. F. Webb, C. J. Anderson, L. Sigal, K. L. Shepard, J. S. Liptay, J. D. Warnock, B. Curran, B. W. Krumm, M. D. Mayo, P. J. Camporese, E. M. Schwarz, M. S. Farrell, P. J. Restle, R. M. Averill, and T. J. Slegel, A 400MHz S/390 Microprocessor, 1997 IEEE International Solid State Circuit Conference Digest of Technical Papers, 1997, pp. 168169, 449.
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C. F. Webb and John Liptay, A High Frequency Custom CMOS S/390 Microprocessor, Proceedings of the 1997 IEEE International Conference on Computer Design, 1997, pp. 241246.
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T. J. Slegel, R. M. Averill, M. A. Check, B. C. Giamei, B. W. Krumm, C. A. Krygowski, W. H. Li, J. S. Liptay, J. D. MacDougall, T. J. McPherson, J. A. Navarro, E. M. Schwarz, K. Shum, and C. F. Webb, IBM's S/390 G5 Microprocessor, presented at the 1998 Hot Chips Symposium, Stanford, CA, August 1998.
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D. Hoffman, R. Averill, B. Curran, Y. H. Chan, A. Dansky, R. Hatch, T. McNamara, T. McPherson, G. Northrop, L. Sigal, A. Pelella, and P. Williams, Deep Submicron Design Techniques for 500MHz IBM S/390 G5 Custom Microprocessor, Proceedings of the 1998 International Conference on Computer Design, 1998, pp. 258263.
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K. L. Shepard, S. M. Carey, E. K. Cho, B. W. Curran, R. F. Hatch, D. E. Hoffman, S. A. McCabe, G. A. Northrop, and R. Seigler, Design Methodology for the S/390 Parallel Enterprise Server G4 Microprocessors, IBM J. Res. Develop. 41, No. 4/5, 515547 (July/September 1997).
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J. Warnock, L. Sigal, B. Curran, and Y. Chan, High Performance CMOS Circuit Techniques for the G4 S/390 Microprocessor, Proceedings of the 1997 IEEE International Conference on Computer Design, 1997, pp. 247252.
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P. Restle, P. Jenkins, A. Deutsch, and P. Cook, Measurements and Modeling of On Chip Transmission Lines Effects in a 400MHz Microprocessor, IEEE J. Solid State Circuits 33, No. 4, 662665 (April 1998).
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A. Dansky, H. Smith, and P. Williams, On-Chip Coupled Noise Analysis of a High Performance S/390 Microprocessor, Proceedings of the 1997 Electronic Components and Technology Conference, 1997, pp. 817824.
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A. Deutsch, W. D. Becker, G. A. Katopis, H. Smith, P. J. Restle, P. W. Coteus, C. W. Surovic, G. V. Kopcsay, B. J. Rubin, R. P. Dunne, T. Gallo, K. A. Jenkins, L. M. Terman, R. H. Dennard, and D. R. Knebel, Design and Technology Guidelines for Short, Medium, and Long On-Chip Interconnections, Proceedings of the 1996 IEEE Electrical Performance of Electronic Packaging Conference, 1996, pp. 3033.
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H. Smith and M. Cases, Wiring Rule Methodology for On-Chip Interconnects, Proceedings of the 1996 IEEE Electrical Performance of Electronic Packaging Conference, 1996, pp. 3335.
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K. L. Shepard and V. Narayanan, Noise in Deep Submicron Digital Design, ICCAD '96 Digest of Technical Papers, 1996, pp. 524531.
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H. H. Chen, Minimizing Chip-Level Simultaneous Switching Noise for High Performance Microprocessors, Proceedings of the IEEE International Symposium on Circuits and Systems, 1996, pp. 544547.
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H. H. Chen and J. S. Neely, Interconnect and Circuit Modeling Techniques for Full-Chip Power Supply Noise Analysis, IEEE Trans. Compon. Packag., Manuf. Technol. 21, No. 3, 209 (August 1998).
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