Introduction

With the continuing application of device scaling, gate oxides below 30 Å will be needed for CMOS devices beyond 0.1 µm. In such small devices, the oxide field reaches a maximum of 5 MV/cm, while the field in silicon exceeds 1 MV/cm [1]. The operation of deep-submicron MOSFETs is now entering a regime in which quantum-mechanical effects become noticeable and classical physics is no longer sufficient for accurate modeling of operating characteristics. The finite thickness of the inversion/accumulation layer (mostly due to quantum-mechanical effects) not only causes a discrepancy between the oxide capacitance and the measured capacitance but also degrades the transconductance [2, 3]. It has been shown that the inversion charge density calculated quantum-mechanically is smaller than that calculated classically for a given gate voltage, thus affecting the shift of the subthreshold curves [4]. As the surface electric field has increased with increased scaling, this has led to increased polysilicon depletion effects [5]. This depletion further reduces the gate capacitance and inversion charge density for a given gate bias. Furthermore, substantial electron tunneling through the gate insulator takes place even at operating bias conditions as low as 1-1.5 V. The gate leakage current increases exponentially as the oxide thickness is decreased. Consequently, future low-voltage circuits may operate with considerable gate-oxide tunneling [6]. With respect to the oxide degradation, hot electrons injected into the gate insulator result in a reduction of device reliability. Therefore, the tunneling characteristics of electrons through ultrathin oxides must be well understood if the technology is to be better understood and controlled.

In this paper, a full quantum-mechanical scheme is developed in order to study the effects described above for ultrathin-oxide MOS structures. The Poisson and the effective-mass Schrödinger equations are solved self-consistently. A transverse-resonant method [7] is utilized to calculate the lifetime associated with the quasi-bound states in the electron accumulation and inversion layers. The tunneling probability associated with the continuum states is also taken into account. Simulated results are compared with experimental results for verification.

Physical models and numerical techniques

•   Schrödinger's and Poisson's equations
When energy bands are bent strongly near a semiconductor-insulator interface, the potential well formed by the interface barrier and the electrostatic potential in the semiconductor can be narrow enough that quantum-mechanical effects become important. Only a given carrier type is treated quantum-mechanically when confined by the surface potential. When electrons are confined, the electrical characteristics of an MOS structure are modeled by solving the coupled effective-mass Schrödinger (in the oxide and silicon regions) and Poisson equations (in the polysilicon, oxide, and silicon regions) self-consistently without taking tunneling current into account [8, 9]:

	–	2	d	1	d	+ V(z) - Ei,j		i,j(z) = 0	(1)
		2	dz	m*i(z)	dz

and

d		(z)	d		(z) =	q	[n(z)-p(z) + NA- - ND+],	(2)
dz			dz			0

where z is the coordinate along the perpendicular direction, m*_i is the electron effective mass in the ith valley, _i,j is the envelope wave function for the jth subband in the ith valley, V is the potential energy, and N_A^- and N_D⁺ are respectively the ionized acceptor concentration and donor concentration. The potential energy V(z) in Equation (1) is related to the electrostatic potential (z) in Equation (2) as follows:

V(z)=-q(z)+EC(z),

(3)

where E_C(z) is the pseudopotential energy due to the band offset at the Si/SiO₂ interface. The wave function (z) in Equation (1) and the electron density n(z) (Si and SiO₂ regions) in Equation (2) are related by

n(z) =	kBT		gim*di		ln[1 + e(EF-Ei,j)/kBT]2i,j(z),	(4)
	2
		i		j

where g_i and m*_di are the ith valley degeneracy and the ith density-of-states effective mass. The basic equations describing hole quantization are similar to Equations (1)-(4). For simplicity, the light and heavy hole bands are also modeled as parabolic, with m*_h,l = 0.20m*₀ and m*_h,h = 0.29m*₀ [10].

The dielectric constant (z) is 11.7 for Si and polysilicon, and 3.9 for SiO₂. The boundary condition at the polysilicon/SiO₂ interface sets electron or hole wave functions to zero; i.e., there is no tunneling current. The electron wave-function solution obtained here is a starting approximation for the next-step electron tunneling current calculation, and the zero-wave-function assumption at the polysilicon/SiO₂ interface will be removed. To accurately model the polysilicon depletion effect, the free-carrier density in the polysilicon region is described by Fermi-Dirac statistics and an incomplete ionization model [11]. The charge-balance equation for heavily doped n-type polysilicon is

2	NC F1/2(f) =	ND	,	(5)
		1 + 2ef

where N_C is the effective density of states at the conduction-band edge, F1/2(_f) is the Fermi-Dirac integral, and _f = (E_F - E_C)/k_BT. Analogous reasoning applies to heavily doped p-type polysilicon.

•   Electron tunneling from quasi-bound states
Many models for the current-voltage characteristics of MOS devices in the direct and the F-N (Fowler-Nordheim) tunneling regimes are available [12-14]. For a two-dimensional gas system of electrons, the tunneling probability, which is applicable only for an incident Fermi gas system of electrons, may no longer be a valid concept. Weinberg [12] proposed a model based on the triangular well approximation and electrons being confined within the lowest subband. However, the contribution from higher subbands was neglected, which might not be entirely correct for the higher temperature. Rana et al. [15] calculated the lifetimes associated with the quasi-bound bands using a path integral expansion of the resolvent operator, which gave quite good results for electron tunneling from an accumulation layer.

For the calculation of the tunneling current from the quasi-bound states at a given bias, the conduction-band profile and the discrete sheet charge densities, previously obtained by assuming _i,j = 0 at the polysilicon/SiO₂ interface, are assumed to be unchanged; i.e., the inversion and accumulation layers act as a reservoir within which the electrons are all in equilibrium with a constant temperature and Fermi level. The closed boundary condition at polysilicon/SiO₂, i.e., _i,j = 0 (assumed in the previous calculation), is relaxed such that the electron wave function is no longer nonzero in the polysilicon gate region. Only the Schrödinger equation throughout the MOS structure (including the polysilicon region) is solved again.

The close analogy between these confined electrons in a varying potential and electromagnetic waves in a wave guide with a varying refractive index provides for the utilization of the transverse-resonant method [7], which is often used for finding the eigenvalue equation for inhomogeneously filled wave guides and dielectric resonators. Consider the conduction-band edge profile shown in Figure 1. The transverse-resonant method defines the intrinsic impedance _l = m*_l/k_l and _l and _l, the terminal impedances for any interface l in which m* is the electron effective mass, k is the wave number, and the arrow superscripts denote looking to the left or looking to the right for any given position. The boundary conditions at interface 1 and interface N - 1 imply that ₁ = 1 and _N-1 = _N. Let region i be approximately the region with the highest electron charge density. We repeatedly apply the transmission-line transformation to express _i in terms of ₁, ₂, · · ·, and _i-1, and similarly for _i in terms of _N-1, _N-2, · · ·, _i+1; i.e.,

m = m	m-1 - jm tan(kmdm)		for m = 2, 3, · · ·, i.	(6)
	m - jm-1 tan(kmdm)

and

m = m+1	m+1 - jm+1 tan(km+1dm+1)		for m = N-2, N-3, · · ·, i.	(7)
	m+1 - jm+1 tan(km+1dm+1)

Figure 1

The final eigenvalue equation for the leaky quasi-bound state follows by imposing the resonance condition

i+i = 0;

(8)

i.e., the input impedance looking to the right must be equal to the negative value of the input impedance seen at this point looking to the left. As a result, we obtain the complex eigenenergy E_i = E_iR - j_i, where the resonance width _i is related to the lifetime of the ith quasi-bound state by

i =		.	(9)
	2i)

The tunneling current density from the ith quasi-bound state is given by

Ji =	Qi	,	(10)
	i

where Q_i is the sheet charge density associated with the ith quasi-bound state.

In the case of three-dimensional (3D) states, the transmission probability through the SiO₂ barrier is a well-defined concept and has a value equal to the ratio of transmitted and incident fluxes. The current density from the 3D states is given [15] by

J3D(Ez)dEz =		qDim*ikBT)	x Ti(Ez) x ln		1 + exp		EF-Ez			dEz,	(11)
		223					kBT
	i

where m*_i is the effective mass, D_i the valley degeneracy associated with the direction i along or across the symmetry axes, k_B the Boltzmann constant, and E_F the Fermi level. The integral has been taken over all states with the same energy E_z in the direction normal to the Si/SiO₂ interface. The transmission probability T_i(E_z) is calculated using the transfer matrix approach [16].

The energy-band structure of SiO₂ is modeled using a Franz-type E(k) dispersion [13] with the effective mass at the conduction-band edge, m* = 0.58m*₀ and 0.55m*₀, in the accumulation and the inversion regions, respectively. The barrier height due to conduction-band discontinuity at the Si/SiO₂ interface is taken to be 3.15 eV. The barrier lowering due to the image force and the conservation of transverse crystal momentum is neglected because it is questionable whether they have any significant effect in the direct tunneling regime of interest here and because none of the existing theories can be readily applied [12].

SiO₂/Si interface quantization effects

Figures 2(a) and 2(b) respectively show the electron and hole distributions in an n⁺-gate/p-Si MOS device. They are calculated using classical [Maxwell-Boltzmann (MB), Fermi-Dirac (FD) statistics] and quantum-mechanical (QM) models. Both the effective inversion and accumulation layer thicknesses in Si are increased by several angstroms owing to quantization effects [8, 9].

Figure 2

•   Oxide thickness determination from C-V
Capacitance-voltage (C-V) characteristics have been used extensively to extrapolate the oxide thickness of MOS devices [17-20]. Thin-oxide MOS capacitance in the strong accumulation region does not saturate but rather increases with gate voltage, as it would for thicker dielectric film. This is partly due to the quantization effects causing the change of the effective thickness of the silicon surface accumulation layer with the gate voltage [see Figure 2(b)] for n⁺-gate/p-Si MOS devices. Figure 3 shows the agreement between the quantum-mechanically calculated and the measured C-V curves of an n⁺-gate/p-Si and a p⁺-gate/n-Si MOS capacitor (t_ox 25 Å). The classical model fails to match the entire range of C-V characteristics regardless of the oxide thickness used. The quantum-mechanical model has proved itself able to fit a full C-V curve of an n-type FET on IBM CMOS 1.8-V, 0.2-µm technology very well, as shown in Figure 4.

Figure 3 Figure 4

On the basis of the quantum-mechanical simulation and experimentally, it was found that the gate capacitance of an n⁺ (p⁺)-gate/p (n)-Si capacitor in the strong accumulation region (typically for an oxide field 3 MV/cm) is insensitive to both the polysilicon and the substrate doping concentrations (Figures 5 and 6), provided that both the substrate and polysilicon are accumulated under the same bias polarity. Therefore, a well-defined QM calculated oxide thickness can be extracted from one measured point in a strong accumulation region, even when the other device parameters are unknown. The QM calculated oxide thickness can be determined from the precalculated oxide thickness versus the measured equivalent oxide thickness curve, as shown in Figure 7. The figure clearly shows that a well-defined oxide thickness can be accurately extracted from the curve independent of polysilicon and substrate doping levels. If the classical models, Maxwell-Boltzmann and Fermi-Dirac statistics, are used instead, the oxide thickness will be overestimated by 2-4 Å as compared with the quantum-mechanical model. Optical measurements have been conducted to verify this extraction scheme. Figure 8 shows that the oxide thicknesses as determined using the above method are within 1 Å of those measured by ellipsometry with multiple measurement angles (wavelength = 6328 Å and index of refraction = 1.458).

Figure 5 Figure 6 Figure 7 Figure 8

•   Threshold voltage shift with high surface field
In the quantum-mechanical treatment, carriers in the inversion layer not only are distributed away from the surface, but also occupy discrete subband energy levels. The inversion carrier sheet densities calculated both quantum-mechanically and classically (FD) for three impurity concentrations (10¹⁷, 5 x 10¹⁷, and 10¹⁸ cm^-3) as a function of gate voltage at room temperature are shown in Figure 9. Since the two lowest subbands (longitudinal and transverse modes) are at finite energies above the bottom of the conduction band, more band bending or a larger surface potential is required to populate the inversion layer. This has the effect of shifting the threshold voltage to a higher value, particularly with high-doping substrate. As the substrate doping increases, the two lowest subband energies increase because of the stronger surface field, and this results in an increasing threshold voltage shift. This shift can be as large as 0.1 V when the substrate impurity concentration reaches 10¹⁸ cm^-3. The threshold voltage shift also increases with the oxide thickness [1, 21].

Figure 9

High substrate doping is needed to suppress the short-channel effects for devices beyond 0.1 µm. It becomes difficult to design a channel profile that controls the short channel while still having a V_T low enough to be compatible with an ~1-V power supply. Therefore, the quantum-effect-induced threshold voltage shift becomes critical in designing deep-submicron devices in which substrate doping >10¹⁷ cm^-3 and surface field >10⁵ V/cm at threshold voltage are required [1].

Finite inversion layer width and polysilicon depletion

Figures 10(a) and 10(b) respectively show the simulated conduction-band edge and the free-electron concentration profiles and C-V characteristics in the inversion region for an n-type MOSFET. The oxide thickness is 25 Å, and the active polysilicon doping concentration is assumed to be 5 x 10¹⁹ cm^-3. The peak electron concentration in the silicon is about 10 Å away from the silicon/oxide interface. Besides, the surface field is very strong, so that there is a 30-Å-wide depletion region around the polysilicon/oxide interface. The two finite capacitances are in series with the oxide capacitance. The difference between the total capacitance and the oxide capacitance due to the two effects becomes more significant with decreasing oxide thickness. Polysilicon depletion effects are directly related to the high fields as well as insufficient activation of dopants at the polysilicon/oxide interface. Even if the polysilicon gate is assumed to behave like a metal gate, i.e., with no polysilicon depletion effect, the difference due to the finite width of the inversion layer only is still 15%. Figure 11 shows the quantum-mechanically simulated C_G/C_ox ratio at V_G = 1.5 V versus polysilicon doping concentration for oxide thicknesses ranging from 15 to 35 Å. Note that as the gate oxide is made thinner, the C_G/C_ox calculated in the inversion region becomes more sensitive to the polysilicon doping concentration. As shown in Figure 5, the results for a given oxide thickness are less sensitive to the polysilicon doping concentration in the accumulation region. This effect has also been studied experimentally using high-frequency C-V curves of both n⁺-polysilicon/n-Si and p⁺-polysilicon/p-Si MOS capacitors for different rapid thermal anneal (RTA) times at 1000°C in Ar, as shown in Figures 12 and 13. The 150-nm polysilicon was implanted to a dose of 3 x 10¹⁵ cm^-2 with P^- at 15 keV for n⁺-polysilicon MOS devices, and B⁺ at 5 keV for p⁺-polysilicon MOS devices. A significant degradation due to polysilicon depletion is found with even ten seconds annealing time. For a 26-Å oxide, the normalized gate capacitance C_G/C_ox of the n⁺-polysilicon MOS device is only 0.7, as opposed to 0.87 expected with no polysilicon depletion. This corresponds to an active phosphorus concentration of only 5 x 10¹⁹ cm^-3 at the polysilicon/SiO₂ interface. The p⁺-polysilicon MOS has about the same active doping concentration at the polysilicon/SiO₂ interface.

Figure 10 Figure 11 Figure 12 Figure 13

Gate direct tunneling current from quantization states

The gate tunneling current, when electrons are confined in the inversion or accumulation layers, is calculated using a transverse-resonant method described in Section 2. The physical oxide thickness is determined using the QM scheme mentioned previously. After the oxide thickness is determined, the polysilicon and the substrate doping concentrations, respectively, can be extracted by fitting the measured C-V curve in the depletion and the inversion regions.

•   Electron tunneling in accumulation and inversion regimes
Figure 14 shows a comparison between the calculated and measured gate tunneling current characteristics of seven p⁺-gate/n-Si p-MOS capacitors (t_ox = 22.9-41.8 Å) in the electron-accumulation region. As the electron accumulation is strong enough, the tunneling current from the free-electron states (3D) is negligible compared with that from quasi-bound states (2D). Figure 15 also shows the excellent agreement between the calculated and the measured I_G-V_G characteristics of six n⁺-gate/p-Si n-FETs (t_ox = 21.9-36.1 Å). More than 90% of the current density comes from the lowest two subbands associated with the twofold-degenerate and the fourfold-degenerate valleys in the conduction band [22]. Simulated I_G-V_G characteristics for oxides down to 15 Å are also shown in Figure 15. In the inversion region, the gate bias of 1.5 V increases by ten orders of magnitude as the oxide thickness decreases from 36 Å to 15 Å. The tunneling current density calculated for a 15-Å oxide agrees reasonably with the reported experimental data [6].

Figure 14 Figure 15

•   Standby power consumption
While the gate leakage current may be at a negligible level compared with the on-state current of a Si MOSFET, it will first have an effect on the chip standby power. Note that the tunneling leakage will be dominated by n-MOS, since p-MOS has a higher barrier for hole tunneling and therefore a lower leakage current. High-performance CMOS logic chips can tolerate a standby power in the 100-mW range. If one assumes that the total active gate area per chip is of the order of 0.1 cm² for future-generation technologies, the maximum tolerable gate current would be of the order of 1 A/cm² for a power supply of 1 V. At higher temperatures (105°C), the tunneling current should be at least ten times lower than the short-channel leakage, since the latter increases rapidly with temperature while the former does not. From Figure 15, it is projected that gate oxide can be scaled to 15-20 Å before running into such a limit. Below 15 Å, however, the oxide tunneling current quickly becomes problematic. Unless a new gate dielectric material is discovered, this sets a limit for bulk CMOS scaling. Dynamic memory devices have a more stringent leakage requirement and therefore a thicker oxide limit.

Conclusions

In this paper, a total quantum-mechanical treatment of accumulated and inverted silicon layers and the electron tunneling current of ultrathin-oxide MOS structures has been presented. A quantum-mechanical scheme is proposed to accurately determine the physical thickness of ultrathin oxides. As the gate length is scaled 0.1 µm, where substrate doping concentration >10¹⁷ cm^-3 or surface field >10⁵ V/cm are required, the shift of the threshold voltage due to the surface quantization becomes substantial. The finite thickness effects degrade the gate capacitance by 13% or more for an oxide thickness of 25 Å or less. Polysilicon depletion effects significantly degrade the capacitance and therefore the transconductance of CMOS devices. It is projected that gate oxides can be scaled down to 15-20 Å in terms of the chip standby power consumption due to direct tunneling currents.

Acknowledgments

The authors wish to thank F. Stern, S. Tiwari, M. Fischetti, K. Han, and E. Wu for many stimulating discussions. They also wish to thank the Yorktown Heights, New York, Silicon Facility and the Advanced Silicon Technology Center (ASTC) in East Fishkill, New York, for device fabrication.

References

Received September 2, 1998; accepted for publication January 29, 1999