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IBM Journal of Research and Development  
Volume 43, Number 3, 1999
Ultrathin dielectric films
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Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations - References

by T. B. Hook, J. S. Burnham and R. J. Bolam

References

  1. S. Hu, ``Vacancies and Self Interstitials in Silicon," Proceedings of the Second Symposium on Defects in Silicon, 1991, pp. 211-236.
  2. S. Hu, ``General Theory of Impurity Diffusion in Semiconductors Via the Vacancy Mechanism," Phys. Rev. 183, No. 3, 773 (1969).
  3. P. Packan and J. Plummer, ``Temperature and Time Dependence of B and P Diffusion in Si During Surface Oxidation," J. Appl. Phys. 68, No. 8, 4327 (1990).
  4. A. Lin, D. Antoniadis, and R. Dutton, ``The Growth of Oxidation Stacking Faults and the Point Defect Generation at the Si-SiO2 Interface During Thermal Oxidation of Silicon," J. Electrochem. Soc. 128, No. 5, 1131 (1981).
  5. T. Matsuoka, S. Taguchi, Q. Khosru, and K. Taniguchi, ``Degradation of Inversion Layer Mobility Due to Interface Traps in Metal Oxide Semiconductor Transistors," J. Appl. Phys. 78, No. 5, 3252-3257 (1995).
  6. L. Perron, A. Lacaita, A. Pacelli, and R. Bez, ``Electron Mobility in ULSI MOSFETs: Effect of Interface Traps and Oxide Nitridation," IEEE Electron Device Lett. 18, No. 5, 235-237 (1997).
  7. F. Gamiz, J. Lopez Villaneuva, J. Banqueri, J. Carceller, and P. Cartujo, ``Universality of Electron Mobility Curves in MOSFETs: A Monte Carlo Study," IEEE Trans. Electron Devices 42, No. 2, 258-265 (1995).
  8. M. Schmidt, F. Terry, B. Malthur, and S. Senturia, ``Inversion Layer Mobility of MOSFET's with Nitrided Oxide Gate Dielectrics," IEEE Trans. Electron Devices 35, 1627 (1988).
  9. P. W. Mertens, M. McGeary, M. Schaekers, H. Sprey, B. Vermeire, M. Depas, M. Meuris, and M. Heyns, ``Effect of Cl in Gate Oxidation," Proceedings of the Symposium on the Science and Technology of Semiconductor Surface Preparation, 1997, pp. 89-100.
  10. Y. Kim, C. Jun, and S. Chung, ``Effects of Chlorine Based Gettering on the Electrical Properties of Rapid Thermal Oxidation/Nitridation Dielectric Films," J. Vac. Sci. Technol. A 11, No. 4, pt. 1, 1039-1043 (1993).
  11. G. Hames, S. Beck, A. Gilicinski, W. Henson, and J. Wortman, ``Influence of HCl on Rapid Thermal Oxides," Proceedings of the Symposium on Rapid Thermal and Integrated Processing V, 1996, pp. 219-224.
  12. B. Vermeire, P. Mertens, M. McGeary, K. Kenis, M. Heyns, M. Schaekers, and A. Lubbers, ``Effect of Different Chlorine Sources During Gate Oxidation," Proceedings of the Second International Symposium on Ultra Clean Processing of Silicon Surfaces, 1994, pp. 143-146.
  13. E. da Silva, Y. Nishioka, Y. Wang, and T. Ma, ``Dramatic Improvement of Hot-Carrier-Induced Interface Degradation in MOS Structures Containing F or Cl in SiO2," IEEE Electron Device Lett. 9, No. 1, 38-40 (1988).
  14. T. Nakanishi, T. Kawamoto, and K. Takasaki, ``Instability of SiO2 Film Caused by Fluorine and Chlorine Inclusion," Jpn. J. Appl. Phys. 1 37, No. 8, 4316-4320 (1998).
  15. A. Balasinski, M. Tsai, L. Vishnubhotla, T. Ma, H. Tseng, and P. Tobin, ``Interface Properties in Fluorinated (100) and (111) Si/SiO2 MOSFETs," Microelectron. Eng. 22, No. 1-4, 97-100 (1993).
  16. T. Ma, ``Metal-Oxide-Semiconductor Gate Oxide Reliability and the Role of Fluorine," J. Vac. Sci. Technol. A 10, No. 4, 469-471 (1992).
  17. T. Lo, W. Ting, D. Kwong, J. Kuehne, and C. Magee, ``MOS Characteristics of Fluorinated Gate Dielectrics Grown by Rapid Thermal Processing in O2 with Diluted NF3," IEEE Electron Device Lett. 11, No. 11, 511-513 (1990).
  18. T. Matsuoka, S. Taguchi, H. Ohtsuka, K. Taniguchi, C. Hamaguchi, S. Kakimoto, and K. Uda, ``Hot-Carrier-Induced Degradation of N2O-Oxynitrided Gate Oxide NMOSFET's," IEEE Trans. Electron Devices 43, 1364-1373 (1996).
  19. A. Uchiyama, H. Fukuda, and T. Hayashi, ``Dual-Gate CMOSFET with N2O-Nitrided Gate SiO2 Film," OKI Tech. Rev. 58, 53-58 (1991).
  20. C. Papadas, G. Ghibaudo, F. Pio, C. Monserie, G. Pananakakis, P. Mortini, and C. Riva, ``On the Charge Build-Up Mechanisms in Gate
    21. Dielectrics," Solid-State Electron. 37, No. 3, 495-505 (1994).
  21. J. Hu, J. Keuhne, T. Grider, M. Rodder, and I. Chen, ``A Comparative pMOS Study of 33Å Nitrided Oxides Prepared by Either N2O or Nitrogen Implant Before Gate Oxidation for 0.18-0.13 mm CMOS Technologies,'' Proceedings of the Symposium on VLSI Technology, Systems, and Applications, 1997, pp. 167-171.
  22. H. Fang, K. S. Krisch, B. J. Gross, C. Sodini, J. Chung, and D. Antoniadis, ``Low Temperature Furnace-Grown Deoxidized Nitrided Oxide Gate Dielectrics as a Barrier to Boron Penetration," IEEE Electron Device Lett. 13, 217-219 (1992).
  23. L. Han, D. Wristers, M. Bhat, and D. Kwong, ``Highly Suppressed Boron Penetration in NO-Nitrided SiO2 for p+ Polysilicon Gated MOS Device Applications," IEEE Electron Device Lett. 16, 319-321 (1995).
  24. D. Lin, J. Cable, and J. Woo, ``Temperature and Electric Field Characteristics of Time-Dependent Dielectric Breakdown for Silicon Dioxide and Reoxidized-Nitrided Oxide," IEEE Trans. Electron Devices 42, 1329-1332 (1995).
  25. Y. Wu and J. Hwu, ``Characterization of Metal- Oxide-Semiconductor Capacitors with Improved Gate Oxide by Repeated Thermal Annealings in N2O," J. Vac. Sci. Technol. B 12, No. 4, 2400-2404 (1994).
  26. J. Ahn, A. Joshi, G. Lo, and D. Kwong, ``Time-Dependent Dielectric Breakdown Characteristics of N2O Oxide Under Dynamic Stressing," IEEE Electron Device Lett. 13, No. 18, 513-515 (1992).
  27. M. Bhat, J. Kim, J. Yan, G. Yoon, L. Han, and D. Kwong, ``MOS Characteristics of Ultrathin NO-Grown Oxynitrides," IEEE Electron Device Lett. 15, No. 10, 421-423 (1994).
  28. T. Hook, K. Watson, E. Lee, D. Martin, R. Ganesh, S. Kim, and A. Ray, ``Correlation Between Fixed Positive Charge and Hot-Electron Immunity for Nitrided Oxides," IEEE Electron Device Lett. 18, No. 10, 471-473 (1997).
  29. A. Philipossian, B. Doyle, and K. Van Wormer, ``Nitrogen Incorporation in Gate Dielectrics: A Correlation Between Auger Electron Spectroscopy and Surface Charge Analysis Techniques," J. Electrochem. Soc. 142, No. 10, L171-L172 (1995).
  30. Z. Ma, Z. Liu, Y. Cheng, P. Ko, and C. Hu, ``New Insight into High-Field Mobility Enhancement of Nitrided-Oxide N-MOSFET's Based on Noise Measurements," IEEE Trans. Electron Devices 41, No. 11, 2205-2209 (1994).
  31. K. Hirabayashi, ``Interface States in Nitrogen Incorporated Gate Oxides," Appl. Phys. Lett. 68, No. 14, 1978-1980 (1996).
  32. N. Saks, D. Ma, and W. Fowler, ``Nitrogen Depletion During Oxidation in N2O," Appl. Phys. Lett. 67, No. 3, 374-376 (1995).
  33. E. Carr, K. Ellis, and R. Buhrman, ``N Depth Profiles in Thin SiO2 Grown or Processed in N2O: The Role of Atomic Oxygen," Appl. Phys. Lett. 66, No. 12, 1492-1494 (1995).
  34. T. Arakawa, R. Matsumoto, and A. Kita, ``Effect of Nitrogen Profile on Tunnel Oxynitride Degradation with Charge Injection Polarity," Jpn. J. Appl. Phys 35, pt. 1, No. 2B, 1491-1495 (1996).
  35. Y. Okada, P. Tobin, V. Lakhotia, W. Feil, S. Ajuria, and R. Hegde, ``Relationship Between Growth Conditions, Nitrogen Profile, and Charge to Breakdown of Gate Oxynitrides Grown from Pure N2O," Appl. Phys. Lett. 63, No. 2, 194-196 (1993).
  36. T. Hook, J. Piccirillo, K. Watson, and E. Nowak, ``A CMOS Technology for a Sub-5-ns 3.3-V LVTTL 1 Mbit SRAM," Proceedings of the European Solid-State Device Research Conference, 1995, pp. 531-534.
  37. D. Grider, S. Hattangady, R. Kraft, P. Nicollian, J. Keuhne, G. Brown, S. Au, R. Eklund, M. Pas, W. Hunter, and M. Douglas, ''A 0.18 µm CMOS Process Using Nitrogen Profile Engineered Gate Dielectrics," Proceedings of the Symposium on VLSI Technology, 1997, pp. 47-48.
  38. J. Hayden, T. McNelly, A. Perera, J. Pfiester, C. Subramanian, and M. Thompson, ``A High Performance 0.25 µm CMOS Technology for Fast SRAMs," Proc. SPIE 2875, 148-163 (1996).
    39. 0.25 µm CMOS Technology with 45Å Nitrided Oxide," Proceedings of the International Electron Devices Meeting, 1995, pp. 691-694.
  39. G. Yoon and Y. Epstein, ``Cycle Time Improvement in Manufacturing Nitrided Gate Oxides for ULSI CMOS Applications," Proceedings of the Advanced Semiconductor Manufacturing Conference, 1996, pp. 186-191.
  40. G. La Rose, F. Guarin, S. Rauch, A. Acovic, J. Lukaitis, and E. Crabbe, ``NBTI Channel Hot Carrier Effects in PMOSFETs in Advanced CMOS Technologies," Proceedings of the 1997 IEEE International Reliability Physics Symposium, 1997, pp. 282-286.
  41. S. Ogawa, M. Shimaya, and N. Shiono, ``Interface-Trap Generation at Ultrathin SiO2 (4-6 nm)-Si Interfaces During Negative-Bias Temperature Aging," J. Appl. Phys. 77, No. 3, 1137-1148 (1995).
  42. E. Poindexter, ``Point Defects and Charge Traps in the Si/SiO2 System and Related Structures,'' Semiconductor Interfaces, Microstructures and Devices: Properties and Applications, Institute of Physics Publishing, Philadelphia, 1993, pp. 229-256.
  43. J. Chun, E. Nowak, L. Ding, and Y. Loh, ``Optimization of Boron Pocket Implantation for Deep Submicron NMOSFET Process," Proceedings of the Fourth International Conference on Solid State and IC Technology, 1995, pp. 224-226.
  44. A. Das, H. De, V. Misra, S. Venkatesan, S. Veeraraghavan, and M. Foisy, ``Effects of Halo Implant on Hot Carrier Reliability of Sub-Quarter-Micron MOSFETs," Proceedings of the 1998 IEEE International Reliability Physics Symposium, 1998, pp. 189-193.
  45. J. Lutze and S. Venkatesan, ``Techniques for Reducing the Reverse Short Channel Effect in Sub 0.5 mm CMOS," IEEE Electron Device Lett. 16, No. 9, 373-375 (1995).
  46. S. Chaudhrya, C. Rafferty, W. Nagy, Y. Chyan, M. Carroll, A. Chen, and K. Lee, ``Suppression of Reverse Short Channel Effect by High Energy Implantation," Proceedings of the International Electron Devices Meeting, 1997, pp. 679-682.
  47. C. Hu, S. Tam, F. Hsu, P. Ko, T. Chan, and K. Terrill, ``Hot-Electron-Induced MOSFET Degradation--Model, Monitor, and Improvement," IEEE Trans. Electron Devices ED-32, No. 2, 375-385 (1985).
  48. R. Wojlter, G. Paulzen, H. Pomp, H. Lifka, and P. Woerlee, ``Three Hot Carrier Degradation Mechanisms in Deep Submicron PMOSFET's," IEEE Trans. Electron Devices 42, No. 1, 109-115 (1995).
  49. S. Jang, T. Tang, Y. Chen, and C. Sheu, ``Modeling of Hot Carrier Stressed Characteristics of Submicrometer pMOSFETs," Solid State Electron. 39, No. 7, 1043-1049 (1996).

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