Biographical sketches of authors

W. W. (Bill) Abadeer   IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (ABADEER at BTVLABVM, abadeer@us.ibm.com). Dr. Abadeer is a Senior Engineer with the SRDC Quality and Reliability group at the Burlington facility. He joined IBM at the Burlington facility in 1976, and has since worked on the reliability of semiconductor devices. Dr. Abadeer received a B.S. in electrical engineering from Assiut University, Egypt, in 1966. From 1966 to 1968 he worked as a teaching assistant at Assiut University. He received his M.S. and Ph.D. degrees in electrical engineering in 1970 and 1976, respectively, from the University of Vermont. Dr. Abadeer is a member of the IEEE and the Electrochemical Society.

Asmik Bagramian   IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (ABAGRAMI at BTVMANVM, abagrami@us.ibm.com). Ms. Bagramian is a Staff Engineer in the ASIC/Custom Qualification Department at the IBM Burlington facility, working on RS/6000 and AS/400 microprocessor product qualifications. She joined IBM in 1984 and was involved with the manufacturing line monitoring strategy for several years. After taking a two-year leave from IBM, Ms. Bagramian received a B.S. degree in electrical engineering from the University of Vermont in 1990. She has received an IBM Outstanding Contribution Award for her effort in the success of the Power-2 Super Chip Products and continues to support the qualification of the new generation of Power Processors.

David W. Conkle   IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (CONKLED at BTVVMOFS). Mr. Conkle is a Staff-level Manager for the Kerf Characterization Department at the IBM Burlington facility. He received a B.S. degree in physics from Sewanee University in 1990 and subsequently joined the United States Navy, where he studied naval nuclear engineering. He left the Navy in 1995 and joined IBM at the Burlington facility in Vermont.

Charles W. Griffin   IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (GRIFFINC at BTVLABVM, griffinc@us.ibm.com). Mr. Griffin is currently with the SRDC Quality and Reliability group at the IBM Burlington facility, focusing on gate dielectric reliability and test structure design. He received his M.S. and B.S. degrees in electrical engineering and a B.A. degree in psychology. Mr. Griffin joined IBM in 1979 at the Burlington facility.

Eric Langlois   Department of Electrical Engineering, Arizona State University, University Drive and Mill Avenue, Tempe, Arizona 85287 (elanglo@asu.edu). Mr. Langlois is currently a Graduate Teaching Associate at the University of Arizona, Tempe, where he is studying for a Ph.D. in solid-state electronics. He received a B.S.E. in engineering physics and an M.S. in electrical engineering from RPI. Mr. Langlois was an IBM employee for 2 years, beginning in 1996. He is a member of Tau Beta Pi.

Brian F. Lloyd   IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (blloyd@us.ibm.com). Mr. Lloyd is a physicist and an Advisory Engineer at the IBM Burlington facility; he is primarily responsible for metal contamination detection and control in semiconductor manufacturing. He is the technical leader of the Electronic Test Center, which performs the metal monitoring measurements for the manufacturing lines. Mr. Lloyd has published on variable retention time characterization and control. He joined IBM in 1980 after teaching and administration at the University of Vermont.

Raymond P. Mallette   IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (mallette@us.ibm.com). Mr. Mallette is currently an Electrical Test Yield Characterization Engineer for microprocessors at the IBM Burlington facility. He received his B.S. degree in physics from San Jose State University in 1985 and his M.S. in electrical engineering from the University of Santa Clara in 1990. Since joining IBM in 1977, he has worked in the Storage Systems Division and, since 1992, in the Microelectronics Division.

James E. Massucco   IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (jmassucco@us.ibm.com). Mr. Massucco is a Staff Engineer in the ASICS Failure Analysis group within the Technology Analysis Project at the IBM Burlington facility. He joined IBM in 1974 after receiving an A.S.E.E. degree from Vermont Technical College. Mr. Massucco has spent his entire career in the failure analysis arena and has worked on various technologies including DRAM, SRAM, ASICS, SiGe, and SOI.

Jonathan M. McKenna   IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (jmmckenn@us.ibm.com). Mr. McKenna is currently an Engineer with the SRDC Quality and Reliability group at the IBM Burlington facility, working on gate dielectric reliability. He joined IBM in 1966 and has been working on gate dielectric breakdown mechanisms and reliability since then. He received his B.S. in electrical engineering from the University of Notre Dame in 1996.

Steven W. Mittl   IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (mittl@us.ibm.com). Mr. Mittl is currently an Advisory Engineer with the SRDC Quality and Reliability group at the IBM Burlington facility, with special interest in NVRAM reliability. He received the B.S. and M.S. degrees in electrical engineering from Lehigh University in 1983 and the University of Vermont in 1986, respectively. He joined IBM at the Burlington facility in 1983 and, since 1986, has been involved in hot-carrier reliability on DRAM and logic technologies, and hot-carrier device and circuit modeling. Mr. Mittl holds a patent on product hot-carrier-reliability test methods; he has authored/coauthored numerous papers on hot-carrier effects.

Philip H. Noel   IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (pnoel@us.ibm.com). Mr. Noel is currently a Staff Engineer in the Technology Analysis Project at the IBM Burlington facility. He joined IBM in 1966 and has worked in failure analysis since 1970. Mr. Noel has been a Group Leader for the DRAM Failure Analysis Team; he is currently the Group Leader for SRAM and CMOS F/A Development.