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Volume 42, Number 6, 1998
Data compression in ASIC cores |
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Table of contents:  HTML ASCII |
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This article: HTML ASCII |
Copyright info |
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A decompression core for PowerPC - Author bios |
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by T. M. Kemp,
R. K. Montoye,
D. J. Auerbach,
J. D. Harper, and
J. D. Palmer |
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References
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http://www.intel.com/intel/museum/25anniv/html/hof/moore.htm.
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The PowerPC Architecture: A Specification for a New
Family of RISC Processors, C. May, Ed., ISBN 1-55860-316-6,
Morgan Kaufmann Publishers, San Francisco, 1994.
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Joint Testing Architecture Group, IEEE Standard No.
1149.1-1990, American National Standards Institute,
Washington, DC, 1990.
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Willard L. Eastman, Abraham Lempel, Jacob Ziv, and
Martin Cohn, “Apparatus and Method for Compressing Data
Signals and Restoring the Compressed Data Signals,” U.S.
Patent 4,464,650, August 7, 1984.
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D. A. Huffman, “A Method for the Construction of
Minimum-Redundancy Codes,” Proc. IRE 40, No. 9, 1098-1101
(1952).
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