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IBM Journal of Research and Development  
Volume 42, Number 6, 1998
Data compression technology in ASIC cores
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Performance as a function of compression - Author bio

by F. A. Kampf

Biographical sketch of author

Francis A. Kampf IBM Microelectronics Division, Burlington facility, Essex Junction, Vermont 05452 (kampf@btv.ibm.com). Mr. Kampf attended Temple University, earning a B.S. in engineering, magna cum laude, in 1987. He joined IBM Kingston in 1988 and participated in the development of an FDDI-based interconnect controller. His continued development effort in the communications interconnect arena resulted in a cooperative effort with the IBM Zurich Research Laboratory and the demonstration of a prototype gigabit WAN/LAN at Telecom'91. He joined the newly formed IBM POWERparallel group in 1992 and participated in the development of the Scalable POWERparallel (SP) line of massively parallel computers. Mr. Kampf's work on the communication subsystem has led to eleven pending patent applications. In 1996, he joined the IBM Blue Logic core development area at IBM Burlington to develop data compression cores. His work includes the development of the JBIG-ABIC and ALDC/BLDC cores.