|
|
 |
|
 |
Volume 41, Numbers 4/5, 1997
IBM S/390 G3 and G4 |
|
Table of contents: HTML ASCII |
|
This article: HTML ASCII |
Copyright info |
 |
 |
 |
 |
| |
|
Standard-cell-based design methodology for high-performance
support chips - References |
 |
by B. Kick,
U. Baur,
J. Koehl,
T. Ludwig,
and T. Pflueger |
 |
 |
 |
References
- TestBench User's Guide, Version 2.1, IBM
Microelectronics Division, Endicott, NY 13760, 1995.
- D. Brand, R. Damiano, L. van Ginneken, and A. Drumm, "In
the Driver's Seat of BooleDozer," Proceedings of the IEEE
International Conference on Computer Aided Design (ICCAD), October
1994, pp. 518-521.
- L. Stok, D. S. Kung, D. Brand, A. D. Drumm, A. J. Sullivan,
L. N. Reddy, N. Hieter, D. J. Geiger, H. H. Chao, and P. J. Osler,
"BooleDozer: Logic Synthesis for ASICs," IBM J. Res. Develop.
40, No. 4, 407-430 (1996).
- EinsTimer User's Guide and Language Reference, Version
1.3, IBM Microelectronics Division, Hopewell Junction, NY 12533,
1995.
- G. Doettling, K. J. Getzlaff, B. Leppla, W. Lipponer,
T. Pflueger, T. Schlipf, D. Schmunkamp, and U. Wille,
"S/390 Parallel Enterprise Server Generation 3: A Balanced System and
Cache Structure,'' IBM J. Res. Develop. 41, No. 4/5,
405-428 (1997, this issue).
- IBM: "CMOS 5X 2.5V Gate Array/Standard Cell,"
http://www.chips.ibm.com/products/asics/tech/cmos5x/.
- C. W. Koburger III, W. F. Clark, J. W. Adkisson, E. Adler, P.
E. Bakeman, A. S. Bergendahl, A. B. Botula, W. Chang, B.
Davari, J. H. Givens, H. H. Hansen, S. J. Holmes, D. V. Horak, C. H.
Lam, J. B. Lasky, S. E. Luce, R. W. Mann, G. L. Miles, J. S. Nakos, E.
J. Nowak, G. Shahidi, Y. Taur, F. R. White, and M. R. Wordeman,
"A Half-Micron CMOS Logic Generation," IBM J. Res. Develop.
39, No. 1/2, 215-227 (1995).
- M. Suzuki, N. Ohkubo, T. Yamanaka, A. Shimizu, and K.
Sasaki, "A 1.5ns 32b CMOS ALU in Double Pass-Transistor Logic,"
Proceedings of the International Solid State Circuits
Conference, 1993, pp. 90-91.
- W. Roesner, "A Hardware Design Language for Logic
Simulation and Synthesis in VLSI," Proceedings of IEEE
COMPEURO, May 1987, pp. 311-314.
- Design Entry: Composer User Guide, Cadence Design
Systems Inc., 555 River Oaks Parkway, San Jose, CA 95134, 1994.
- A. Kuehlmann, A. Srinivasan, and D. P. LaPotin,
"Verity--A Formal Verification Program for Custom CMOS Circuits,"
IBM J. Res. Develop. 39, No. 1/2, 149-165 (1995).
- W. Roesner, "A Mixed Level Simulation System for VLSI Logic
Designs," Proceedings of IEEE COMPEURO, May 1987, pp. 196-199.
- W. G. Spruth, The Design of a Microprocessor,
Springer-Verlag, Berlin, 1989.
- J. Vygen, "Algorithms for Large-Scale Flat Placement," to
be published in Proceedings of the 34th Design Automation
Conference, 1997.
- J. Vygen, "Algorithms for Detailed Placement of Standard
Cells," to be published in Proceedings of Euro-DAC 1997.
- R.-S. Tsay, "An Exact Zero-Skew Clock Routing Algorithm,"
IEEE Trans. Computer-Aided Design 14, No. 12, 242-249
(February 1993).
- K. D. Boese and A. B. Kang, "Zero-Skew Clock Routing Trees
with Minimum Wirelength," Proceedings of the ASIC
Conference, 1992, pp. 17-21.
- U. Fassnacht and J. Schietke, "Timing Analysis and
Optimization of a High Performance CMOS Processor Chipset," to be
published in Proceedings of Euro-DAC 1997.
- A. Hetzel, "A Sequential Detailed Router for Huge Grid
Graphs," to be published in Proceedings of Euro-DAC
1997.
- T. Stoehr, M. Alt, A. Hetzel, and J. Koehl, "Analysis,
Reduction and Avoidance of Crosstalk on VLSI Chips," to be published
in Proceedings of Euro-DAC 1997.
- D. J. Hathaway, R. R. Habra, E. C. Schanzenbach, and
S. J. Rothman,
"Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology,"
IBM J. Res. Develop. 40, No. 4, 453-460 (1996).
- K. Sato, M. Kawarabayashi, H. Emura, and N. Maeda,
"Post-Layout Optimization for Deep Submicron Design,"
Proceedings of the 33rd Design Automation Conference, 1996,
pp. 740-745.
- D. Greenhill, E. Anderson, J. Bauman, A. Charnas, R.
Cheerla, H. Chen, M. Doreswamy, P. Ferolito, S. Gopaladhine, K. Ho, W.
Hsu, P. Kongetira, R. Melanson, V. Reddy, R. Salem, H. Sathianathan, S.
Shah, K. Shin, C. Srivatsa, and R. Weisenbach, "A 330 MHz 4-Way
Superscalar Microprocessor," Proceedings of the International
Solid State Circuits Conference, 1997, pp. 166-167.
- M. R. Choudhury and J. S. Miller, "A 300 MHz CMOS
Microprocessor with Multi-Media Technology," Proceedings of the
International Solid State Circuits Conference, 1997, pp. 170-171.
- A. K. Jain, R. P. Preston, P. J. Bannon, M. S. Bertone, R.
P. Blake-Campos, G. A. Bouchard, D. S. Brasili, D. A. Carlson, R. W.
Castelino, K. M. Clark, S. Kobayashi, B. P. Lilly, S. Mehta, B. S.
Miller, R. O. Mueller, A. Olesin, Y. Saito, and V. Yalala,
"1.38cm² 550MHz Microprocessor with Multimedia
Extensions," Proceedings of the International Solid State
Circuits Conference, 1997, pp. 174-175.
- E. B. Eichelberger and T. W. Williams, "A Logic Design
Structure for LSI Testability," Proceedings of the 14th Design
Automation Conference, 1977, pp. 462-468.
- Cordt W. Starke, "Design for Testability and Diagnosis
in a VLSI CMOS System/370 Processor," IBM J. Res. Develop.
34, No. 2/3, 355-362 (1990).
- R. Ihle and C. W. Starke, "Array Built-In Selftest for a
S/390 Microprocessor Chipset," Proceedings of the European Test
Conference, 1997, pp. 97-100.
- R. W. Bassett, M. E. Turner, J. H. Panner, P. S. Gillis,
S. F. Oakland, and D. W. Stout,
"Boundary-Scan Design Principles for Efficient LSSD ASIC Testing,"
IBM J. Res. Develop. 34, No. 2/3, 339-354 (1990).
- "IEEE Standard Test Access Port and Boundary-Scan
Architecture," IEEE Standard 1149.1-1990, IEEE Standards Board, 345
E. 47th St., New York, NY 10017, 1990.
- P. S. Gillis, U. Baur, K. McCauley, and F. Woytowich, "Delay
Test of Chip I/Os Using LSSD Boundary Scan," to be published in
Proceedings of the International Test Conference, 1997.
|
 |
|
|