Biographical sketches of authors
William V. Huott IBM System/390 Division,
522 South Road, Poughkeepsie, New York 12601
(ace@vnet.ibm.com). Mr. Huott is an Advisory Engineer in S/390
custom microprocessor design. He received a B.S. in electrical
engineering from Syracuse University in 1984. Mr. Huott is a design
engineer responsible for the definition and design of the memory array
built-in self-test (ABIST) circuitry and interfaces for high-frequency
custom microprocessors. He is also responsible for the engineering test
debug of high-frequency custom macros and support chips. Mr. Huott
joined IBM in 1983 at the East Fishkill facility designing, testing,
and debugging high-speed logic gate arrays and memory arrays. He holds
four U.S. patents and several publications.
Timothy J. Koprowski IBM System/390
Division, 522 South Road, Poughkeepsie, New
York 12601 (tkoprowski@vnet. ibm.com). Mr. Koprowski is
an Advisory Engineer in S/390 custom microprocessor design. He received
his B.S. in electrical engineering from Lehigh University in 1981 and
is currently pursuing an M.S. degree in computer engineering at
National Technological University. He is a design engineer responsible
for the definition and design of the LBIST circuitry for high-frequency
custom microprocessors. Mr. Koprowski joined IBM in 1981 at the East
Fishkill facility, where he designed advanced VLSI logic and memory
test systems for eleven years. He holds one U.S. patent.
Bryan J. Robbins IBM System/390 Division,
522 South Road, Poughkeepsie, New
York 12601 (brobbins@vnet. ibm.com). Mr. Robbins
received the B.S. degree in electrical engineering from Purdue
University in 1986, and the M.S. degree in computer and electrical
engineering from Purdue University in 1988. He is an Advisory Engineer
responsible for test modeling and test generation for high-frequency
custom microprocessors. Mr. Robbins joined IBM in 1988 at Poughkeepsie,
New York.
Mary P. Kusko IBM Microelectronics
Division, East Fishkill facility, Route 52,
Hopewell Junction, New York 12533 (mkusko@vnet.ibm.com). Ms.
Kusko is an Advisory Engineer in EDA (electronic design automation).
She received a B.S. in electrical engineering from the University of
Delaware in 1982, joining the IBM S/390 Division that same year. From
1982 to 1993 she held several positions in processor design. Since
1993, she has worked in the areas of test strategy definition and
implementation, model generation, test analysis, test generation, and
internal test tool direction. Ms. Kusko is a member of the IEEE, SWE,
and TTTC.
Stephen V. Pateras LogicVision Inc., 101
Metro Drive, Third Floor, San Jose, California
95110 (pateras@lvision.com). Dr. Pateras received his Ph.D.
degree in electrical engineering from McGill University in 1991. While
at IBM, he served as test team leader in the S/390 custom
microprocessor group. He is now Director of System BIST Product
Engineering at LogicVision. Dr. Pateras is a member of the IEEE and has
authored or coauthored several papers and articles in the fields of
test generation and BIST.
Dale E. Hoffman IBM System/390 Division,
522 South Road, Poughkeepsie, New York
12601 (daleh@vnet.ibm.com). Mr. Hoffman received a B.S. in
electrical engineering from Pennsylvania State University in 1981, and
an M.S. in electrical engineering from Syracuse University in 1984;
he is currently pursuing an M.S. in computer engineering at National
Technological University. He is a Senior Engineer and a design manager
responsible for test, chip integration, physical design, and back-end
design methodology for high-frequency custom microprocessors. Mr.
Hoffman joined IBM in 1981 at the East Fishkill facility, where he
designed and managed advanced VLSI logic and memory test systems for
eleven years. He holds five U.S. patents and has several publications.
Timothy G. McNamara IBM System/390
Division, 522 South Road, Poughkeepsie, New
York 12601 (tmcnamera@vnet.ibm.com). Mr. McNamara is
an Advisory Engineer in S/390 custom microprocessor design. He
received his B.E. in electrical engineering from the State University
of New York at Stony Brook in 1983 and his M.S. in computer engineering
from Syracuse University in 1990. He is currently working on
high-performance clock system designs for S/390 CMOS microprocessors.
Mr. McNamara holds two U.S. patents.
Tom J. Snethen IBM Microelectronics
Division, 1701 North Street, Endicott,
New York 13760 (snethent@endvm5.vnet. ibm.com). Mr.
Snethen is a Senior Engineer in the IBM Test Design Automation
project. He received the B.S.E.E. degree from the University of
Missouri and the M.S.E.E. from MIT before joining IBM in 1965. Mr.
Snethen is a member of the IEEE. He holds one patent and has authored
or coauthored several papers in the field of fault modeling and test
generation.
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