Introduction: Lithographic scaling

k/NA,

k/NA²,

k, k

During the last ten years, image resolution was sufficiently increased to scale minimum dimensions from 1-µm feature sizes for the 1Mb DRAM devices to 0.25-µm features for the 256Mb DRAM. The depth of focus is proportional to the inverse of the square of the numerical aperture; thus, if resolution is enhanced by increasing NA, the depth of focus becomes very small. If the resolution is enhanced by decreasing the wavelength, the corresponding decrease in depth of focus is less severe. As shown in Figure 1 for lithography at the diffraction limit, a shorter wavelength provides more depth of focus at a particular resolution value because the shorter wavelength allows a lower-NA photolithography tool to achieve equivalent resolution.

Figure 1

The IBM Microelectronics Division has been active in the evolution of lithography throughout the development of the semiconductor industry (Figure 2). DRAM production of 64Kb devices utilized scanning exposure equipment operating at a G-line wavelength of 436 nm. These tools were capable of operating at several different exposure wavelengths, including 436 nm, 313 nm, and 245 nm [1]. IBM used these tools for 256Kb DRAM chips by formulating a resist, TNS, which was functional at the 313-nm exposure region [2], allowing the critical feature size to be scaled from 2 µm to 1.4 µm. This approach was repeated for 1Mb DRAM chips, and a 245-nm exposure region was used to obtain the 1-µm critical features with the same tool set, which required the development of the first production deep-UV (DUV) chemically amplified, negative-tone resist [3]. At this time, G-line steppers were introduced at a NA of 0.35, and the process for the production of 1Mb DRAM reverted to G-line lithography. For the 4Mb DRAM generation, stepper technology was extended by scaling the wavelength to the I-line ( = 365 nm). High-NA (0.42-0.45) G-line steppers were used to manufacture 4Mb pilot line products at 0.8-µm ground rules, while lower-NA (0.35) I-line steppers were used for final qualification of products with 0.6-0.7-µm critical features. For the 16Mb generation, DUV in the 245-nm exposure region was utilized for development and initial production, while very high NA (0.5-0.6) I-line (365 nm) was used for volume production at 0.4-0.5-µm image sizes. The 64Mb and 256Mb DRAM generations use high-NA (0.5-0.6) DUV tools at = 248 nm for images at 0.25-0.35-µm resolution.

Figure 2

During this scaling process, several DUV resist materials were developed and utilized by IBM. While I-line resists were composed of modified G-line materials, the DUV resists operated by a different mechanism. The DUV region of the mercury arc lamp is of relatively low intensity compared to the I-line and G-line regions. To compensate for low DUV exposure intensities, a chemical amplification method [4,5] was used to enhance the speed of the DUV resist. This catalytic amplification process, combined with new resins that were less absorbing at = 245 nm than the traditional novolak materials, introduced significantly different resist processing requirements for DUV lithography. These unique process requirements were characterized and included as part of the process of implementing DUV lithography in product applications.

DUV processing for product applications

The initial DUV resist formulation was a negative-tone material with a new resin, solubility inhibitor, photoactive compound, and developer solution compared to the previously utilized mid-UV resists. The resin was a para-hydroxy-styrene polymer (PHOST) modified with a tertiary-butoxy-carbonyl (tBOC) functionality to impart insolubility in polar solvents and aqueous-base solutions. A sulfonium salt was used as a photo-acid generator, and a post-exposure bake was used to cause a catalytic cleavage of the tBOC group from the exposed resist (Figure 3) [4,6]. Development in anisole of the exposed and baked resist selectively removed the unexposed material, providing a negative-tone image.

Figure 3

This resist was very sensitive, requiring a 1-5-mJ/cm² exposure dose, depending on the formulation and process conditions. Contrast was high, with a value of 8-10, and the 1-µm resolution requirement of this product application was easily achieved. With this system, throughput levels of 100 wafers per hour could be achieved with existing scanning exposure equipment. However, a number of difficulties with this system soon became apparent as product application work progressed. While resist adhesion was acceptable on silicon wafers, poor adhesion was obtained on the silicon nitride product film. The hexamethyldisilazane (HMDS) adhesion priming operation, which was effective for conventional development of resists in aqueous solutions, was ineffective for the hydrophobic solvent used in this DUV develop process. Thermal oxidation at the nitride surface to form a silicon oxynitride surface improved resist adhesion sufficiently to warrant further product development.

Metallic oxide residues were identified in the resist stripping baths and traced to the photosensitizer materials used in the DUV resist. These residues were reduced by specifying smaller wafer batches between bath changes and, ultimately, by replacing the metallic components in the resist formulation with organic materials.

Attention also focused on control of the post-exposure bake process, because this parameter became more important for linewidth control than exposure dose levels in the photolithography tool (Figure 4). The catalytic chemical amplification reaction which produced the high resist sensitivity needed for operation at the low light intensities available in DUV was exponentially dependent on the bake temperature used to induce the catalysis. As a result, resist sensitivity also became exponentially dependent on the bake temperature [7].

Figure 4

Not only was the catalytic amplification process of this resist dependent on the bake conditions, but it could also be affected by the presence of contaminants from chemicals in the manufacturing environment. It was observed that freshly coated wafers, when placed in a cassette on the photolithography tool and exposed in sequence, often displayed a continuous shift in linewidth from wafer to wafer across the cassette. The resist steadily became one to three times less sensitive as the delay time from application of resist to its exposure increased. After two to three hours, the resist stabilized at a lower sensitivity value (Figure 5) This behavior was caused by the absorption of chemical bases, such as N-methylpyrolidone (NMP), into the resist at part-per-billion levels, which interrupted the catalytic image formation process [8] and caused a large change in resist sensitivity. Initially, wafers were deliberately allowed to stand in the manufacturing environment and absorb the chemical contaminants. The resist sensitivity became relatively stable and then could be processed with acceptable linewidth control after the contaminants were absorbed. Because of variations in the manufacturing environment, however, significant shifts in resist sensitivity were observed for each subsequent batch of product wafers. This required "send-ahead" wafers to control image size for each lot, thereby significantly reducing throughput from the DUV sector (Figure 6)

Figure 5 Figure 6

While these difficulties rendered the process cumbersome, the development cycle of the 1Mb DRAM proceeded on schedule, and initial product demand was supplied. Several million fully functional 1Mb DRAM chips were produced with DUV (245-nm) technology.

In the laboratory, the negative-tone resist used on the 1Mb DRAM was shown to act as a positive-tone material if an appropriate polar developer was used [4]. In practice, the positive-tone image was distorted by an insoluble film at the surface of the exposed resist (Figure 7). After the experience with the negative-tone resist, it was realized that this inhibition effect was caused by chemical contamination inadvertently poisoning the resist, and that a suitable positive-tone image could be formed if the effect of this contamination process was reduced or eliminated. When the resist was formulated to provide a higher dissolution rate of unexposed resist, the surface layer of contaminated resist could be removed in the development process, and a resist image with an acceptable profile was obtained.

Figure 7

As work on the 1Mb DRAM production shifted to more advanced G-line steppers (0.35 NA), the DUV effort was refocused on the 16Mb DRAM and the development of a positive-tone material which would overcome the limitations of this first-generation negative-tone DUV resist.

16Mb DRAM: Positive-tone DUV resist, 1987-1992
The experience gained from the 1Mb DRAM DUV development effort was used as a foundation for 16Mb DUV applications. When the 16Mb work began in 1987 at 500-nm resolution, conjecture centered on whether conventional optical lithography with single-layer resist processing would be attainable at the reduced depth-of-focus margins, or whether bilayer and top-surface imaging resists would be required [9]. At this time, I-line steppers were barely achieving the 0.7-µm resolution requirements of the 4Mb DRAM. A new DUV photolithography tool with a NA of 0.36 (discussed below in the section on photolithography tools) was developed which was suitable for 0.5-µm lithography. This tool was used for the 16Mb DRAM development program.

The 16Mb DRAM had six critical mask levels with resolution requirements of 0.5-0.6 µm and an overlay tolerance of 0.2 µm. Several of these levels contained critical features which were small openings (0.5-0.6 µm) printed in a field of resist. A positive-tone resist was desirable for these levels because of an enhanced focus window compared to negative-tone imaging and reduced reticle defects. (The positive-tone reticle was primarily a chrome area, which would mask particulates on the reticle surface, whereas a negative-tone reticle would have been mostly clear, allowing particles on the reticle to print as defects.) The negative-tone resist formulation used for the 1Mb DRAM was modified to create a positive-tone resist that overcame many of the initial DUV process control problems. The resin composition was modified to reduce loss of mass by decreasing the concentration of solubility inhibitor (which provided increased etch resistance and reduced image distortion) and to reduce the resist contrast. Reduced contrast allowed the resist to be more robust to chemical contamination by an airborne organic base. This, in turn, allowed aqueous-base developers to be used without adverse effects on the positive-tone resist profile. Resist chemical amplification was reduced by using lower post-exposure bake temperatures and adding acid-quenching materials to the resist during formulation. While resist sensitivity was reduced by these changes, process latitude with respect to profile and sensitivity variations caused by unintended interruption of the chemical amplification process was increased. The use of aqueous-base developer allowed conventional HMDS surface treatments to be used for the enhancement of resist adhesion, thereby avoiding problems with lifting and cracking resist. Resin molecular weight was sharply reduced, which enhanced depth of focus and resulted in an absence of resist residuals after development. Nonmetallic photosensitizers were implemented, which further reduced residuals after resist-stripping processes. In addition, bottom antireflective coatings (ARC) and topcoat materials were developed to provide barriers to chemical contamination from both the wafer substrate and the processing atmosphere. As a result, the chemical amplification process in the resist could proceed without unintended interruption. These enhancements provided sufficient process stability for development and fabrication of the 16Mb critical mask levels. Since resist stability was sufficient, exposure dose could be controlled with statistical process control (SPC) charts rather than with send-ahead test wafers (Figure 8) [10]. The exposure dose was modified only if the average image size for a lot was outside the indicated control limits, or if seven lots in succession were above or below a target image size. The process steps for the first-generation positive-tone DUV resists are as follows:

• Adhesion prime or ARC apply/bake.
• Apply resist.
• Bake.
• Apply topcoat.
• Bake.
• Expose.
• Post-exposure bake.
• Develop in aqueous base.

Figure 8 Figure 9

Figure 10

While the formulation changes for the 16Mb application of DUV resist relieved many of the initial problems, a continuing concern was the dependence of sensitivity on the post-exposure bake temperature (Figure 11). When more than one resist bake plate was used in a "clustered process," maintaining the temperature matching of the plates was often difficult. In a clustered process, the bake station is physically attached to the photolithography tool, and it is desirable to use a sufficient number of bake plates to match the throughput capability of the photolithography tool. In this arrangement, different bake plates are often used for successive wafers as they emerge from the photolithography tool. Gradual drift in bake-plate temperature could cause variation in wafer-to-wafer or lot-to-lot linewidth. Defects at the resist bake step, either from particles lodged between the wafer and the surface of the bake plate, or from failure of the positioning pins on the hot plate, could cause linewidth variation within a wafer. Prototype linewidth monitoring equipment was developed to monitor the image formation on a bake plate, both as a potential means of controlling the photolithographic-image size and as a means of detecting excursions in the bake process (Figure 12) [11], but are not implemented in manufacturing at present. The second-generation positive-tone DUV resist materials which are currently appearing in the marketplace provide more stability in the post-exposure bake process, as well as stability to airborne chemical contamination [12].

Figure 11 Figure 12

Logic gate conductor: 1992-1994
During the characterization of the DUV positive-tone resist process, systematic within-chip differences in printing were observed. At the memory gate conductor level, in particular, isolated lines in the support areas were consistently wider than corresponding nested lines in a memory array. Because of the timing circuits which are present in the gate conductor features, this systematic difference caused yield reductions due to a loss in chip performance (Figure 13) [13]. For the memory product, this linewidth deviation can be caused by both systematic etch and photolithography causes (Figures 14 and 15) [13(b)]. Polymer by-products of an etch plasma deposit more rapidly on the isolated features than the nested features, thereby causing the isolated lines to become wider than the nested lines[14]. The diffraction effects of the positive-tone aerial image caused the resist to print with a similar systematic bias, with isolated lines printing approximately 8% larger than nested lines. For the memory product, it was possible to optimize the reticle image size compensations to reduce this effect by using manual image inspection and compensation procedures. For logic applications, however, the irregular nature of the circuit pattern was too complex for manual alteration, and the features could not be automatically compensated with the available software technology.

Figure 13 Figure 14
Figure 15

The aerial image of negative-tone lines contains a minimal offset between nested and isolated lines [15]. In fact, the isolated lines print slightly smaller than the nested lines for negative-tone resist (Figure 15). This aids in compensating for the etch effect, which can be modified with etch chemistry and process, but which generally causes isolated lines to increase in width compared to nested lines for polysilicon etch processes (Figure 14).

A second-generation negative-tone resist was formulated to further enhance the DUV process capability [16]. This resist was used with a 0.5-NA step-and-scan exposure tool to achieve 0.35-µm gate conductor lithography. The mechanism of this resist is different from the initial DUV material in that the resin is cross-linked to impart insolubility to the exposed area. The previous resist had used a polarity change of the resin to impart insolubility to the exposed area. This new approach allowed a resist to be formulated which could be developed with an aqueous base, providing the good adhesion characteristics obtainable with such systems. Cross-linking in this resist is very efficient, providing high-speed resist materials. As a result, chemical additives can be used to stabilize the resist to chemical amplification poisons without degrading the resist sensitivity or reducing wafer throughput. This negative-tone resist does not require a topcoat for process stability.

The cross-linking mechanism also provides a low-activation-energy image-formation process during the post-exposure bake. This results in a smaller variation of image size with post-exposure bake temperature, thereby further enhancing the manufacturability of DUV processes. Developer process latitude is also enhanced, since the image size for negative-tone resist is considerably more stable to develop time than for positive-tone resists.

The use of this resist, combined with enhanced etch processes and reticle uniformity, led to improvements in across-chip linewidth control for CMOS logic gate conductor programs. This enhanced linewidth control provides higher performance and yield values, which are the primary components for process manufacturing costs (Figure 16) [12,13].

Figure 16

While the photoresists described were largely developed at IBM, an essential component in chip fabrication for device applications is the exposure tool used to image the semiconductor patterns into the resist. During this application activity, IBM interacted closely with equipment suppliers to ensure that both the resist process and tool capabilities were commensurate with product requirements.

Evolution of DUV photolithography tool

Figure 17

The tool is adapted to DUV exposures using a filter in the illuminator/condenser. Since the illumination source is broadband and the reflective projection optics are corrected to less than 240 nm, resolutions of 1 µm needed for 1Mb DRAM manufacturing could be achieved. This scanner was used in the 1Mb DRAM application described earlier.

The use of this tool at resolutions below 1 µm was not pursued because astigmatism was not fully corrected in some systems, and vertical and horizontal lines could differ by as much as 0.2 µm for a nominal 1.0-µm feature. Also, exposure uniformity was difficult to achieve because the DUV illumination was not centered in the scanned slit.

1985 to 1992
As the 16Mb DRAM development program was initiated, there was a need for resolutions of 0.5 µm, the introduction of larger product chips, and the use of 200-mm wafers. This led IBM to acquire a tool from Perkin-Elmer designed specifically for DUV. This was the first tool (Table 1) based on the step-and-scan principle [17]. In tools of this type, the wafer is stepped to a new field, which is then scanned; this continues until all fields have been scanned (Figure 18).

Figure 18

Tools of the step-and-scan type are attractive for microlithography because they are able to print large fields at high wafer throughputs. Good resolution and low distortion can be obtained because the scanned field is small compared to the printed field and can be well corrected optically at higher NA values. Good linewidth control and overlay can be obtained because focus and alignment can be adjusted during the scan of each field to match the topography and previous level pattern. With a bright illumination source, high throughput can be achieved because the stage can be scanned at high speeds.

The first step-and-scan tool from the Silicon Valley Group [18] required a 2.4-kW lamp and an arcuate light tunnel to provide a high-intensity uniform exposure dose at full scan speed. The 0.35-NA projection optics are of the reflective ring-field type with 4× magnification capability added (Figure 19). In practical implementation, lenses are added for aberration correction. The alignment of the projection optics required a specially developed DUV interferometer to reach diffraction-limited performance.

Figure 19

A novel permanent magnet planar motor system and air-bearing wafer stage were developed to step and scan the wafer at velocities of 50 to 65 mm/s. The reticle and wafer stage were synchronized by master-slave servo control to ±40 nm. Through-the-lens viewing was implemented at the 488-nm and 512-nm argon laser lines to provide flexibility against thin-film interference effects. Active vibration isolation and temperature-controlled, chemically filtered air were provided to limit environmental influences on the projection optics and wafer.

This tool achieved a DOF greater than ±0.75 µm at a resolution of 0.5 µm. Full-field distortion was measured at 70 nm, and overlay capability on oxide wafers of 150 nm (98%) was achieved by using six-field global fine alignment. Product overlay performance for manufacturing tools of this type was 120 nm to 200 nm depending on the level. In production, the step-and-scan tool was capable of several hundred wafers per day and achieved reliability in excess of 200 hr mean time between fails (MTBF).

A 0.42-NA DUV Nikon stepper (Table 1) was also used for applications with ground rules of 0.5 µm or less. The all-quartz refractive lens of this tool required a <3-pm-bandwidth excimer laser illumination source because of the single-material optical design. An advanced Cymer laser source was required for pulse-to-pulse stability and dose accuracy. The condenser optics relied on a fly's-eye lens and a vibrating mirror to achieve dose uniformity and low speckle. The condenser optics were pressurized slightly to prevent the accumulation of airborne contaminants on the lens surfaces.

This tool achieved a DOF of approximately 1.0 µm at a resolution of 0.45 µm and an overlay of <150 nm on product. The DUV stepper, which provided reliable production capacity, has a throughput of approximately two hundred wafers per day.

1993 to 1995
A 0.5-NA DUV step-and-scan tool (Table 1) was developed for resolutions of 0.35 µm and smaller [19]. The optics and development of the optional off-axis broadband viewing system represent significant changes from the original step-and-scan tool. A fly's-eye lens and light polarization are used to more than double the uniform exposure power to 20 mJ/cm². The 5-mm-by-22-mm rectangular scanned field is produced using a compact beam-splitter cube design [19] (Figure 20). Through-the-lens viewing was improved and an off-axis viewing system added to provide viewing at higher NA with broadband illumination.

Figure 20

This tool achieves a DOF of ±0.40 µm at a resolution of 0.35 µm and a full-field distortion that is significantly lower at 35 nm. Global fine alignment achieves an overlay of 90 nm on oxide films and a product overlay of 90 to 150 nm depending on the level.

Beyond 1996
Step-and-scan tools equipped with a 0.6-NA lens for 0.25-µm resolution will soon be the standard DUV tool. A high-repetition-rate excimer laser exposure source for these tools will provide enough power to expose less sensitive resists at higher stage speeds. The 0.6 NA will provide 0.25-µm images, but with a very small (0.4-µm) depth of focus. The use of off-axis illumination and variable should partially alleviate the depth-of-focus limitations. Overlay will be improved because optical distortions become smaller, and better viewing and stage capabilities will be available. Wafer throughputs and productivity will improve because the stages are being driven faster.

Lithography outlook: 1996-2000

Acknowledgments

References

Received February 9, 1996; accepted for publication December 2, 1996