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Volume 40, Number 4, 1996
IBM ASIC design and testing |
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Table of contents:  HTML |
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Copyright info |
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PowerPC AS A10 64-bit RISC microprocessor |
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by J. W. Bishop, M. J. Campion, T. L. Jeremiah, S. J. Mercier, E. J. Mohring, K. P. Pfarr, B. G. Rudolph, G. S. Still, and T. S. White |
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The PowerPC AS™ A10 64-bit RISC microprocessor is a
4.7-million-transistor integrated circuit design, using IBM CMOS 5L
0.5-µm, 3-V, four-level-metal ASIC technology. Support
for the PowerPC AS architecture is implemented in a
213-mm2; die using a semicustom design methodology. Chip
density and speed are enhanced through the use of custom macros and
multiport arrays. An on-chip phase-locked-loop circuit is used
to reduce chip-to-chip clock skew. Full utilization of the
four-level-metal interconnect technology was achieved through
architectural floorplanning, performance clustering, and timing-driven
placement and wiring, with a total wire length of over 102 meters
placed on the 14.6 × 14.6-mm die. The microprocessor is a
pipelined, superscalar design with five separate functional units, a
4KB instruction cache, and an 8KB data cache. The design includes
parity, error-correction, and error-logging functions, as well as
self-test for logic and arrays during power-on. The design is robust
and implements a wide range of performance configurations at the system
level, allowing direct attachment of DRAM to the processor, or
high-performance L2 cache options using high-speed SRAM. An on-chip
system I/O bus and bus controller are provided for attachment of
peripherals.
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