POWER2: Next generation of the RISC System/6000 family
by S. W. White and S. Dhawan
Since its announcement, the IBM RISC System/6000* processor has
characterized the aggressive instruction-level parallelism
approach to achieving performance. Recent enhancements to the
architecture and implementation provide greater superscalar
capability. This paper describes the architectural extensions
which improve storage reference bandwidth, allow hardware
square-root computation, and speed floating-point-to-integer
conversion. The implementation, which exploits these extensions
and doubles the number of functional units, is also described.
A comparison of performance results on a variety of industry
standard benchmarks demonstrates that superscalar capabilities
are an attractive alternative to aggressive clock rates.
*IBM and RISC System/6000 are trademarks or registered trademarks of International Business Machines Corporation.
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