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Volume 38, Number 5, 1994
POWER2 and PowerPC architecture |
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Table of contents:  HTML |
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DOI: 10.1147/rd.385.0503 |
Copyright info |
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POWER2 fixed-point, data cache, and storage control units |
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by D. J. Shippy and T. W. Griffith |
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The POWER2* fixed-point, data cache, and storage control units
provide a tightly integrated subunit for a second-generation
high-performance superscalar RISC processor. These functional
units provide dual fixed-point execution units and a large
multiported data cache, as well as high-performance interfaces
to memory, I/O, and the other execution units in the processor.
These units provide the following features: dual fixed-point
execution units, improved fixed-point/floating-point
synchronization, new floating-point load and store quadword
instructions, improved address translation, improved fixed-point
multiply/divide, large multiported D-cache, increased bandwidth
into and out of the caches through wider data buses, an improved
external interrupt mechanism, and an improved I/O DMA mechanism
to support multiple-streaming Micro Channels.*
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*IBM, RISC System/6000, AIX, POWER Architecture, PowerPC, PowerPC Architecture, PowerPC 601, PowerPC 603, PowerPC 604, PowerPC 620, POWER2, POWER Parallel SP2, and Micro Channel are all trademarks or registered trademarks of International Business Machines Corporation.
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