The high performance of pipelined, superscalar processors such
as the POWER2* and PowerPC* is achieved in large part through
the parallel execution of instructions. This fine-grain
parallelism cannot always be achieved by the processor alone,
but relies to some extent on the ordering of the instructions in
a program. This dependence implies that optimizing compilers
for these processors must generate or schedule the instructions
in an order that maximizes the possible parallelism. This paper
describes the parts of the TOBEY compiler which address the
instruction scheduling issue.
*IBM, RISC System/6000, AIX, POWER Architecture, PowerPC, PowerPC Architecture, PowerPC 601, PowerPC 603, PowerPC 604, PowerPC 620, POWER2, POWER Parallel SP2, and Micro Channel are all trademarks or registered trademarks of International Business Machines Corporation.
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