by J. I. Barreh, R. T. Golla, L. B. Arimilli, and P. J. Jordan
This paper describes the instruction cache unit (ICU) of the IBM
POWER2* processor, with emphasis on improvements over the
original POWER ICU design. The POWER2 ICU incorporates a new
compare-branch scheme that minimizes processing time penalties,
a second branch processor, increased branch look-ahead
capability, and doubled instruction-fetch and instruction-
dispatch bandwidth.
*IBM, RISC System/6000, AIX, POWER Architecture, PowerPC, PowerPC Architecture, PowerPC 601, PowerPC 603, PowerPC 604, PowerPC 620, POWER2, POWER Parallel SP2, and Micro Channel are all trademarks or registered trademarks of International Business Machines Corporation.
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