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Exploiting heterogeneous multi-core processor systems for high-performance network processing
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by H. Franke,
T. Nelms,
H. Yu,
H. D. Achilles,
and R. Salz
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In this paper, we examine two network-processing appliances,
i.e., the IBM ProventiaA Network Intrusion Prevention System and
the IBM WebSphere® DataPower® service-oriented architecture
appliance, and the specific requirements they pose on emerging
heterogeneous multicore-processor systems. We first describe the
function and architecture of these applications. Next, we describe the
computational requirements imposed on the applications as a result
of the expectation that they operate at the maximum transmission
rate on high-speed networks (i.e., on networks at speeds greater than
10 Gb/s) with minimal latency. Given that next-generation systems
will provide on-chip and off-chip hardware acceleration functions,
we identify and quantify the functions that can be offloaded onto
hardware accelerators to provide latency reduction by more efficient
execution, increased concurrence, or both. Referring to models of
specific hardware accelerators, we estimate and quantify the impact
on the performance of the applications. We conclude with a
discussion of the modifications to these applications that are required
to exploit the large number of hardware threads and accelerators
available on emerging multicore-processor systems.
 Full paper
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