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IBM Journal of Research and Development

IBM z10 System   Abstract
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Packaging design of the IBM System z10 Enterprise Class platform central electronic complex

by J. G. Torok
F. E. Bosco
W. L. Brodsky
E. F. Furey
G. F. Goth
D. J. Kearney
J. J. Loparco
M. T. Peets
K. L. Pizzolato
D. W. Porter
G. Ruehle
and W. H. White
The IBM System z10™ Enterprise Class mainframe addresses the modern data center requirements for minimizing floor space while increasing computing power efficiency. These objectives placed challenges on the z10™ packaging design as a result of significantly increased demand on system packaging density, power delivery, and logic and power cooling efficiency compared with the recent IBM System z9® and z990 mainframe generations. Several innovations were implemented to successfully meet these challenges: a more powerful multichip module (MCM) that delivers denser computing capability and a 64-way system; a vertically mated processor unit (PU) book structure that achieves a more efficient thermal implementation and a higher signal bandwidth between processors; and a PU book-centric dc–dc power delivery design that is more efficient. This paper presents the key elements to achieve this design: the novel mechanical load transmission paths and the connector technologies for the MCM, PU book, I/O, and power regulation components; an innovative cooling and thermal design that includes component-level tolerance of failures; and improved power delivery and power code developments to maximize the overall z10 compute efficiency.

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