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IBM Journal of Research and Development

IBM z10 System   Abstract
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Design and verification of the IBM System z10 I/O subsystem chips

by T. Schlipf
M. M. Helms
J. Ruf
M. Klein
R. Dorsch
B. Hoppe
W. Lipponer
S. Boekholt
T. Röwer
M. Walz
and S. Junghans
In this paper, we discuss the microarchitecture, design, and verification of two IBM System z10™ I/O (input/output) chips: the z10™ hub chip, an InfiniBand™ host channel adapter with IBM-proprietary enhancements, and the InfiniBand memory bus adapter (MBA) chip, an InfiniBand-to-self-timed-interface fanout chip for attaching legacy I/O. Designing and verifying these chips presented many challenges. We describe our transaction- and packet-tracking concepts and the use of communication groups that emulate the behavior of logical partitions and their role in handling error and recovery cases. A novel technique has been employed to ensure that design implementation and architectural register definitions are consistent in a fully automated approach. Finally, we describe our approach to improving self-test coverage, which is based on an automated process of test-point insertion.

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