|
|
|
Functional verification of the IBM System z10 processor
|
|
|
by C. A. Krygowski
D. G. Bair
R. M. Gott
M. H. Decker
A. V. Giri
C. Habermann
M. Heizmann
S. Letz
W. J. Lewis
S. M. Licker
H. Mallar
E. C. McCain
W. Roesner
N. Siddique
A. E. Seigler
B. W. Thompto
K. Weber
and R. Winkelmann
|
|
|
|
|
|
This paper describes the comprehensive verification effort of the IBM System z10™ processor chipset, which consists of the z10™ quad-core central processor chip and the companion z10 symmetric multiprocessor (SMP) chip. The z10 processor chipset represented a significant redesign of its predecessor and thus presented a new challenge to ensure complete functional correctness of the product before the construction of actual system hardware. The z10 microprocessor pipeline was completely redesigned to support a doubling of the operating frequency. It also includes new hardware performance features, such as enhanced branch prediction, a reoptimized cache hierarchy, hardware-based prefetching, and a hardware implementation of decimal floating-point arithmetic in IEEE formats. In addition, there were significant hardware changes in the SMP storage hierarchy for optimized data latency performance. These changes include a new system topology, interprocessor book protocol, larger SMP size, and various aggressive cache ownership schemes. Key verification innovations are described, and a direct relationship to improved z10 system quality is provided for most cases.
 Full paper
|
|
|
|
|
|
|
|
PDF
