IBM System z10 performance improvements with software/hardware synergy
by K. M. Jackson, U. Hild, M. A. Wisniewski, S. Heisig, D. Schmidt, P. Yeh, and W. Gellerich
This paper describes efforts to more fully exploit the synergy
potential between hardware and software to improve performance
on the IBM System z® platform. Although the IBM commitment
to upward compatibility for System z mainframes prevents us
from engaging in hardware generational tuning, software stack
improvements aimed at one generation of hardware tend to
increase in value for subsequent generations. This paper presents
some of the software synergy efforts that were made to complement
hardware design characteristics to improve performance and
that will continue to be of benefit in future machine generations.
Also presented is IBM z/OS® HiperDispatch management, which
minimizes cache coherency penalties when dispatching work,
and the new IBM System z10™ hardware instrumentation, the
central processor measurement facility (CPMF), which supports
software performance optimizations by providing counters and
sampling and allowing the software to measure central processor
activities to determine hotspots. The CPMF is nondisruptive, has
low overhead, and can run in multiple logical partitions
simultaneously.
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