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POWER™, an acronym for Performance Optimization With Enhanced RISC, is an architecture designed by IBM that is based on the reduced instruction set computer (RISC) philosophy. The RISC microprocessor CPU design recognizes a relatively limited number of instructions that can be quickly executed.
More particularly, the POWER4™ chip, released in 2001, was a computer processor that implemented the IBM POWER and 64-bit PowerPC® instruction-set architectures. The POWER4 became the first microprocessor to incorporate dual cores in a single die, and it was also the first to implement a multichip module (MCM), which contains four POWER4 microprocessors in a single package. POWER4 was designed to address both commercial and technical workloads, and it leveraged IBM technology using an 0.18-μm-lithography copper and silicon-on-insulator (SOI) technology. The POWER4 design was initially introduced at processor frequencies of 1.1 GHz and 1.3 GHz, which surpassed other 64-bit microprocessors in certain key performance benchmarks.
This very highly cited paper describes the objectives that were established for the POWER4 design, and it discusses the components of the resultant system from a microarchitecture perspective. POWER4 refers not only to a chip, but also to the structure used to interconnect chips to form the system. Thus, the paper also describes the processor and interconnection architecture employed to form systems comprising up to a 32-way symmetric multiprocessor.
From an interesting historical standpoint, note that in 2002, the year this paper was published, IBM produced the IBM eServer™ p670, a mid-range server with POWER4 microprocessor technology that cost “up to 34 percent less than comparable Sun Microsystems' machines.” In the same year, IBM demonstrated “the scalability of the IBM eServer p670 and its AIX operating system by supporting a record 12,600 users of the Oracle® E-Business Suite….”
In 2005, a substantial part of Volume 49 (No. 4/5) of the IBM Journal of Research and Development was devoted to POWER5™ system architecture, virtualization, operating systems, design verification, and performance.
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