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The interconnects that carry electrical signals between computer chips and packages often distort such signals, and voltage coupling between signals may prevent the logical circuits from giving the correct results because of the unwanted interference. Additionally, power supply voltages may be affected by the switching of logical circuits that together may switch hundreds of amperes of current in a high-performance computer. This leads to unacceptable fluctuations in the supply voltages that may make the logical circuits fail. These kinds of problems are reduced to acceptable limits by designing the chip and package layouts using sophisticated electrical analyses and tools.
This highly cited IBM Journal paper describes research that was the basis for a new approach to the modeling of integrated circuits. Hundreds of subsequent papers describe research based on this approach. More particularly, the work provides the foundation for Partial Element Equivalent Circuit (PEEC) modeling for electronic chips and packages.
In the early 1960s, the role of inductance in electronic circuits and digital systems was often limited to discrete components, and the coupling among these components was often ignored. In the microcircuit environment, however, complicated multiconductor structures served as interconnections. The electrical characterization of such structures became especially important because coupled voltages, signal delays, and signal distortion all degrade system performance. Analysis of the electrical properties of multiconductor systems is also fundamental to system optimization. To address many of these challenges, this paper introduced a comprehensive theory of partial inductance in which the calculations are based on inductance loop segments.
The technique has been applied extensively in IBM and has resulted in several popular software programs, such as L3D, which are based on its concept. L3D has served IBM from the 1970s into the 1990s as the key program for inductance calculations; during this time, most of the IBM high-end single- and multi-chip packages were designed using the tool. Today, other programs based on the PPEC approach are used at IBM to solve electrical packaging problems.
From an academic point of view, the basic methods described in this paper have been the topics of several Ph.D. dissertations and of discussion in many books. The work has led to several awards including the prestigious Richard R. Stoddart Award from the IEEE EMC Society. This work has also spawned other IBM Journal papers based on this approach for the modeling of integrated circuits. These papers are listed in the related links section.
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