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Using advanced compiler technology to exploit the performance of the Cell Broadband Engine™ architecture
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by A. E. Eichenberger,
J. K. O'Brien,
K. M. O'Brien,
P. Wu,
T. Chen,
P. H. Oden,
D. A. Prener,
J. C. Shepherd,
B. So,
Z. Sura,
A. Wang,
T. Zhang,
P. Zhao,
M. K. Gschwind,
R. Archambault,
Y. Gao,
and R. Koo |
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The continuing importance of game applications and other numerically intensive workloads has generated an upsurge in novel computer architectures tailored for such functionality. Game applications feature highly parallel code for functions such as game physics, which have high computation and memory requirements, and scalar code for functions such as game artificial intelligence, for which fast response times and a full-featured programming environment are critical. The Cell Broadband Engine™ architecture targets such applications, providing both flexibility and high performance by utilizing a 64-bit multithreaded PowerPC® processor element (PPE) with two levels of globally coherent cache and eight synergistic processor elements (SPEs), each consisting of a processor designed for streaming workloads, a local memory, and a globally coherent DMA (direct memory access) engine. Growth in processor complexity is driving a parallel need for sophisticated compiler technology. In this paper, we present a variety of compiler techniques designed to exploit the performance potential of the SPEs and to enable the multilevel heterogeneous parallelism found in the Cell Broadband Engine architecture. Our goal in developing this compiler has been to enhance programmability while continuing to provide high performance. We review the Cell Broadband Engine architecture and present the results of our compiler techniques, including SPE optimization, automatic code generation, single source parallelization, and partitioning.
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IBM Systems Journal, Volume 45, Issue 1, pp. 59-84 (2006).
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The Cell Broadband Engine™ microprocessor was jointly developed by Sony, Toshiba, and IBM. This microprocessor was designed to bridge the gap between conventional desktop processors and more specialized high-performance processors. Additionally, the processor has potential for use in digital distribution and entertainment systems—as well as for scientific imaging systems and physical simulations. Because game applications often feature highly parallel code for physical simulations and graphical realism, game developers require fast response times and a full-featured programming environment. The Cell Broadband Engine architecture targets such applications, providing both flexibility and high performance by using a 64-bit multithreaded PowerPC® processor element (PPE) with two levels of globally coherent cache and eight synergistic processor elements (SPEs).
This paper addresses an ongoing critical technical challenge in which the growth in processor complexity drives the need for sophisticated compiler technology. Thus, the paper has the potential for wide general interest. The authors present several compiler techniques designed to exploit the performance potential of the SPEs and to enable the multilevel heterogeneous parallelism found in the Cell Broadband Engine (BE) architecture. Note that the Cell BE system has two distinct processor types, each with its own application-level instruction-set architecture (ISA). One ISA (for the PPE) is the familiar 64-bit PowerPC with a vector multimedia extension unit (VMX). The second ISA (for the SPEs) is a 128-bit SIMD instruction set for multimedia and general floating-point processing. Typical applications on the Cell BE processor use code to exploit both of these processors.
This paper is also notable because of the market it addresses, and the need to deliver vast computational capability for online games. The global games and interactive entertainment industry is expanding rapidly. Industry revenues were estimated at $28 billion for 2004 and are anticipated to double by 2008. The various requirements of online games, such as scalability, full immersion, and raw performance, will continue to grow for many years.
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