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Before this paper was published, floating-point processors were usually considered as options that could be added to the main CPU of mainframes for performing scientific applications. This paper describes a way in which floating-point processing became an integral part of the CPU for an IBM System/390® by implementing the unit in one CMOS VLSI chip. This paper is notable in that it describes the first time that a floating-point processor had been implemented in a single chip for an IBM mainframe. The work was also significant because it allowed the complete mainframe to be packaged in a much smaller area.
These and related efforts at IBM represented a turning point in mainframe evolution, marking the first time that a mainframe was completely implemented in CMOS technology. Water-cooled systems now moved to air-cooled systems that needed only one-tenth of the installation area and three percent of the energy of previous related systems. In the early 1990s, customer concerns regarding cost, floor space, maintenance, and energy utilization led some industry pundits to predict the demise of the mainframe “dinosaur.” However, the kind of work described in this paper played an important role in impressing the world with the viability of the mainframe.
Note that a paper published in 1999 describes the S/390® floating-point unit (FPU) on the fourth-generation (G4) CMOS microprocessor chip, which had dimensions of 17.35 by 17.30 mm [E. M. Schwarz, L. Sigal, and T. J. McPherson, “CMOS floating-point unit for the S/390 Parallel Enterprise Server G4,” IBM Journal of Research and Development, Vol. 41, No. 4/5, pp. 475-488 (1997)]. One copy of the FPU, including the dataflow and control flow but not including the FPR register file, had dimensions of 5.3 by 4.7 mm. Two FPU copies existed on the chip for error-detection purposes.
Another paper, published in 1997, highlights the key steps taken by IBM to transform the S/390 mainframe platform and to enhance customer satisfaction with improvements in cost, scalability, and application enablement [G. S. Rao, T. A. Gregg, C. A. Price, C. L. Rao and S. J. Repka, “IBM S/390 Parallel Enterprise Servers G3 and G4,” IBM Journal of Research and Development, Vol. 41, No. 4/5, pp. 397-403 (1997)]. In the transition of S/390 systems from bipolar to CMOS technology, rapid improvements in the circuit density and performance of CMOS allowed IBM to produce four generations of S/390 CMOS systems from 1994 to 1997. In addition to increases in processing capacity of the S/390 CMOS-based systems, Rao et al. note that an even more dramatic improvement was made in the reliability of the systems. The authors note that “Reliability enhancement through a) improved intrinsic failure rates of CMOS technology versus bipolar; b) extensive reductions in the total number of parts required for the CMOS systems…; and c) continued improvements in fault-tolerant design [redundancy, ECC, cache-line delete, sparing, and N + 1 power (an extra power supply)] resulted in an improvement of nearly two orders of magnitude in MTBF (mean time between failures)” of one of the current CMOS mainframes of the time with respect to a corresponding bipolar system.
The IBM Journal of Research and Development has had a long history of reporting on mainframe hardware evolution. See, for example, the “IBM eServer z990” issue (Vol. 48, No. 3/4, 2004), the “IBM eServer z900” issue (Vol. 46, No. 4/5, 2002), and the “System-on-a-Chip/Packaging” issue (Vol. 46, No. 6, 2002).
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