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In 1990, IBM introduced the RISC System/6000®—a family of nine workstations that were among the fastest and most powerful in the industry. The RISC System/6000 used reduced instruction set computer technology, a computer design pioneered by IBM that simplifies processing steps to speed the execution of commands, and Advanced Interactive Executive (AIX™), the IBM implementation of the UNIX™ operating system. Throughout the 1990s, IBM continued to develop the RISC System/6000 family with new, faster models with more features. The RISC System/6000 SP™ line of supercomputers, for example, have been used in such tasks as improving weather and climate forecasting, simulating nuclear explosions, and defeating World Chess Champions.
This paper provides an early overview of the RISC System/6000 hardware with its highly concurrent superscalar second-generation CPU RISC engine that was based on the IBM Power Architecture™. The platform combines the powerful RISC architecture with sophisticated hardware-design techniques to achieve a short cycle time and a low cycles-per-instruction (CPI) ratio. Reliability, availability, and serviceability (RAS) were major considerations in the design of the processor. All of the chip-to-chip data buses had parity, and the memory bus had error detection and correction (ECC) and bit steering.
This paper also describes the electronics that are distributed among the CPU, I/O, and standard I/O planars. The Micro Channel® interface from the CPU is attached to the I/O planar, where it is buffered and feeds eight I/ O slots. Additionally, the paper discuses the RISC System/6000 central electronics complex, which contains several semicustom chips: an instruction-cache unit, a fixed-point unit, a floating-point unit, four data-cache units, a storage control unit, an input/output interface unit, and a clock chip. Packaging technologies are discussed.
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