VLSI on-chip interconnection performance simulations and measurements

IBM Journal of Research and Development, Volume 39, Issue 4, pp. 383-401 (1995).

This highly cited paper by Edelstein et al. is the result of a careful analysis of the options available to minimize delays due to interconnections and choice of materials in future semiconductor integrated circuits. Using simulations, the authors demonstrate how geometry, material properties, and processing details affect the performance of on-chip interconnects. To reduce line resistance, replacing Al/Cu lines with Cu lines and a low-ε dielectric and the use of “fat” wires to reduce long-line resistances are among the choices to reduce power or improve performance in future CMOS chips. It is noted that although the proposed measures will slow power escalation, they do not provide long-term solutions, since materials limits for lower resistivity and dielectric constant will be reached and further reduction will not be feasible.