Overview

IPCMOS (Interlocked Pipelined CMOS) is a circuit technique suitable for multi-GHz operation. It achieves robust operation at high speeds by providing both forward and reverse interlocks on locally generated clocks. A test site using a cross-section of the compressor tree of a floating point multiplier has been fabricated which demonstrates operation at frequencies as high as 4.5 GHz in 0.18-micron 1.5-V bulk CMOS technology. In addition to providing very high clock rates, IPCMOS allows simplified latch structures and significant power reduction.