Overview
The size and complexity of modern hardware systems have turned the functional verification of these systems into a mammoth task. Verifying such systems involves tens or hundreds of person years and requires the computing power of thousands of workstations. But even with all this effort, it is virtually impossible to eliminate all bugs in the design before it tapes out. In fact, statistics show that close to 50% of chips require additional unplanned tape-outs because of functional bugs. Moreover, in many cases, project plans call for several planned tape-outs at intermediate stages of the project before the final release of the system. As a result, an implementation of the system on silicon running at real-time speed is available. This silicon is used, among other things, as an intermediate and final vehicle for functional validation of the system in a process known as post-silicon validation.
In recent years, we have seen increasing evidence that pre- and post-silicon verification cannot achieve their goals exclusively-pre-silicon, in terms of finding all the bugs before tapeout, and post-silicon, in terms of finding the bugs that escaped pre-silicon. This creates an increasing need to bridge the gap between these two domains by sharing methodologies and technologies, allowing easier integration between the domains.
The focus of this activity is the stimuli generation aspect of a unified pre- and post-silicon methodology. We utilize many of the concepts and technologies that make constrained random test generators successful in pre-silicon verification for the post-silicon domain. Specifically, we are developing a user-directable tool that uses declarative test templates for post-silicon validation, similar to those used in Genesys-Pro.