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Physics-based On-chiP Parameterized INterconnect Suite (POPPINS)

Analog and Mixed Signal Technologies

Patents

  • D. Goren et al, An Interconnect-Aware Methodology for Integrated Circuit Design, Patent Number 10/091,934 filed on March 6 (2002).
  • D. Goren et al, "Interconnect-Aware integrated circuit design" Pat. No. 10/723,752 filed November 26 (2003).
  • R. Gordin and D. Goren, "Modeling Capacitance of On-Chip Coplanar Transmission Lines over the Silicon Substrate ", Patent Number 04101861 (UK), filed May 7 (2004).
  • D. Goren, J. D. Katzenstein and Y. V. Tretiakov, "Method for Determining Fringing Capacitances on Passive Devices within an Integrated Circuit", Filed as Docket BUR920040085US1 on July 16 (2004).
  • D. Goren et al, "Device and method for reducing dishing of critical on-chip interconnect lines", Patent Number 10/954,672, filed 30 September (2004).
  • D. Goren et al, "Integrated Circuit Transformer Devices for On-Chip Millimeter-Wave Applications", filed as docket YOR920040637US1 on April 8 (2005).
  • D. Goren and S. Shlafman, "Capacitance Modeling", Patent Number 11/153047 filed 15 June 2005 (IBM docket No. IL9-2005-0025).