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Physics-based On-chiP Parameterized INterconnect Suite (POPPINS)

Analog and Mixed Signal Technologies

Overview

Physics-based On-chiP Parameterized INterconnect Suite

In multi-GHz chip design domains, interconnects are becoming the limiting factor in the performance, energy dissipation, and signal integrity. The demanding requirements from on-chip wiring pose a serious problem, both from the design flow and the modeling aspects. Previous attempts to tackle this problem in analog and mixed signal (AMS) designs and most other silicon chip technologies are based on the post-layout extraction approach, which fails in the multi-GHz domain for several reasons.

  1. The interconnect impact is considered too late in the design flow, which may cause costly reroutes and redesigns.
  2. The attempts to develop RCL post-layout extraction methods usually fail to correctly determine the wire inductances, due to inability to determine the correct current return paths.
  3. The existing RC(L) extraction tools do not take into account several physical effects, such as substrate effects, which can have a significant impact on the design performance.

The other existing solution in typical GaAs based microwave designs, models each and every wire by its full frequency domain S-parameters, which is simply not practical for the silicon based larger designs. Besides, this approach makes every wire or device be impedance matched to 50 Ohm, which is not possible in most silicon based design domains.

In 1998, in IBM Haifa Research Labs, a team led by David Goren started developing a new approach to interconnect problem, which was born as an attempt to resolve serious signal integrity issues in certain SiGe technology designs. The idea of the proposed approach is that since inductance related effects are important only for a relatively small number of critical wires in a given design, these lines can generally be identified at the pre-layout design stages. The critical wires are then designed differently, using a unique set of transmission line devices, "on-chip T-lines". The team introduced a small set of on-chip T-lines configurations which cover most of AMS design needs, and developed original semi-analytical models which predict their full frequency dependent behavior from DC up to the cut-off frequency of the transistors in the given technology (skin and proximity effects, silicon substrate effects, crossing lines impact, etc.). An extensive set of measurements was performed on a large combination of on-chip T-lines, and showed good agreement in the whole range of frequencies from DC up to millimeter wave frequencies (110GHz.for microstrip T-lines).

Until 2004, the team had focused on ultra high speed A&MS designs in IBM SiGe technology, for which the microstrip T-line devices had been introduced. Later on, they moved their focus to mainstream high speed digital designs in CMOS technologies, for which coplanar T-line devices and compact RC wire models were introduced, both supporting crossing lines, which complement the design solution to be the "Interconnect Design Suite" offering.

As the result of cooperation with the IBM Burlington design enablement department, the T-line devices have become an integral part of IBM design kits (DK's) in SiGe technologies delivered to both external and internal customers. Since 2005, they will be included also in IBM DK's for leading CMOS and SOI technologies.

In addition to the IBM DK activities, the team performs development and delivery of the T-line models directly to IBM main internal customers.

The T-lines give the IBM semiconductor technology a clear competitive advantage over other foundries - they provide a comprehensive design solution for on-chip interconnects.