Piparazzi generates an architectural test that stimulates a specific predefined micro-architectural event in a specific micro-processor pipeline. A pipeline is a structure that has a fetch unit, a prefetch unit, a decode unit, a dispatcher unit, a sequence unit, several execution units (fixed point units, floating point units, load/store units, branch units) and a completion unit. Piparazzi is not limited to the above units; on the contrary, the actual pipeline is modeled for Piparazzi.
The user specifies micro-architectural events in terms of predefined properties. Piparazzi supports a rich set of such properties, and the event is defined by specifying relationships between them. The language by which these relationships are specified includes standard arithmetic, logical quantifiers, and bit manipulation operators. The same language is also used internally to model the micro-architecture.
There are several classes of such properties:
- Timing properties - the dispatch cycle, the issue cycle, and the number of cycles an instruction is stalled in a stage, etc.
- Flow properties - the execution pipeline, the program order, the dispatcher's slot, and the branch prediction, etc.
- Architectural properties - opcodes of instructions, the instructions operands' data, and the effective and real address of a memory access instruction, etc.
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