With the silicon technology roadmap reaching nano-scale levels, the complexity involved in the design of low power/low voltage circuits is having a dramatic effect on design productivity and turnaround time. To reduce the effort involved in the design-from-scratch approach, in many cases the design is based on a similar working design from a different technology. This approach has the benefit of proven design robustness and performance. Since the design intended for the new technology process is based on a working design and shares the topology of the original design, automation can further reduce the design effort.
IBM Device Level Analog Circuit Migration Tool is a new productivity tool to assist design teams in the task of process migration. It is based on device-level information such as performance and operation conditions, which are gathered from the source technology design. The information is stored in a database and used to set targets (performance and operating conditions) at the device level for the target technology design, enabling automation of the resizing task. The device-level approach enables fast and efficient convergence, even for very large circuits.
The tool has been used successfully in several migration projects, including 90nm bulk to 65nm bulk, 90nm SOI to 90nm bulk, 65nm SOI to 45nm SOI, 45nm SOI to 32nm SOI, and 32nm SOI to 22nm SOI. A partial list of circuits that were migrated using the tool includes PLLs, IOs, CML circuits, static CMOS control logic, moderate speed static and dynamic logic, band-gap references, operational amplifiers, comparators, FIR filter, 50 Ohm differential output drivers, current distribution mirrors, peak detectors, multiplexers, and additional analog periphery modules covering all typical significant analog circuitry in the digital chip. The tool has been used on large circuits including a complete 6GHz and 11GHz high speed transmitter slice composed of over 500 leaf cells with thousands of devices.
The main benefits of using the tool:
- Fast migration of large circuits
- Significant savings in time and resources
- Automatic handling of the myriad of differences between the source and target processes, including process, design kit, device set, and device parameter
- Accurate mapping and scaling of bias conditions with great accuracy
- Extensive set of design migration quality measurements within the tool
- Automatic correction upon model changes, changes in resistor values, transistor model of gm, gds, and Vt, etc.
The tool is integrated in the Cadence environment and supports all relevant IBM technologies. A working version of the tool is available for independent design groups with appropriate licensing.