Genesys Back to Haifa Departments Verification Background Functional verification is widely recognized as the bottleneck of the design development cycle. This is due to a combination of several correlated factors: the exponential increase in design complexity, tighter time-to-market requirements, and higher quality expectations. In parallel, verification means are not evolving at a matching pace. The cost of the late discovery of bugs is enormous, which justifies the fact that, for a typical microprocessor design project, more than half of the overall resources spent are devoted to its verification. In general, functional verification is done using two different methodologies: formal verification and verification by simulation of test programs. The formal verification approach attempts to prove the correctness of properties on the design. While it is promising, it is of limited application due to problems of state explosion when applied on large design blocks. Verification by simulation checks the behavior of the design with selected input stimuli called test programs. This approach requires a means to produce the test programs in large quantities and at high quality. This is usually provided by an automatic random test generator.