Publications
Overview
- Constraint-based Random Stimuli Generation for Hardware Verification (AI Magazine Fall 2007)
Verification experience
- Industrial Experience with Test Generation Languages for Processor Verification (DAC 2004)
- Addressing Test Generation Challenges for Configurable Processor Verification (HLDVT 2006)
- VLIW - A Case Study of Parallelism Verification (DAC 2005)
In depth
- Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification (IEEE Design & Test of Computers 2004)
- DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms (HLDVT 2006)
- Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture (IEEE Transactions on Parallel and Distributed Systems May 2003)
- Generating Concurrent Test Programs with Collisions for Multiprocessor Verification (HLDVT 2002)
- Adaptive Test Program Generation: Planning for the Unplanned (HLDVT 2002)
- Improving Test Quality Through Resource Reallocation (HLDVT 2001)
Historical insight
- Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator (DATE 1999)
- Test Program Generation for Functional Verification of PowePC Processors in IBM (DAC 95)
- Model Based Test Generation for Processor Verification (IAAI 94)