The ever-growing demand for performance and time-to-market, coupled with the exponential increase in hardware size, has made the verification task increasingly difficult. This problem is exacerbated by low tolerance for bugs in CPU designs.
The elusive nature of hardware bugs and the amount of stimuli needed to cover the scenarios specified in the verification plan, has made directed random stimuli generation the verification approach of choice.
Former solutions, including directed testing and hand-tailored project-specific generators, are not scalable to today's challenges.
Commercial verification environments have added constructs to support reuse and random generation. However, effective application of these generic features to processor verification requires significant investment in infrastructure and methodology.