Genesys Back to Haifa Departments Major Properties Genesys enables the creation of programs ranging from completely deterministic to totally random programs. By the means of a directives file, control is given to guide the generation to the desired extent, while any parameter not explicitly constrained is randomly set to any consistent value. The ability to target the whole range of test randomness is of key importance for implementing the proposed methodology. Namely, the methodology induces the creation of fully random tests, specific scenarios, and test templates with varying levels of randomness. The control over test generation is mainly achieved by two control mechanisms: Instruction Control: which controls the selection of instructions Resource Control: which offers control over the architecture resources Another major feature of Genesys is its ability to easily acquire additional testing knowledge (TK). The incorporation of TK into a random generator enables the user to adjust the distribution of the probability of the targeted test space. As a simple example, the result of zero for an ADD instruction is typically of special importance, while the relative probability of its random occurrence is practically non-existent. Informing the test generator that the result of zero is important, and should thus be generated with a reasonable probability. This is an example of the process used to add TK to the generator. As a more advanced example, many architectures define instructions with two memory operands (e.g., string instructions in x86). Having the two memory locations overlap is usually an exceptional event rarely occurring randomly, and worthwhile to add as TK to the generator. More generally, adequate weights should be given to corner cases, which would otherwise occur with negligible probability. In Genesys, TK is in the form of generation and validation functions (written in C) and is held in the external specification model. The most noteworthy property of Genesys is that this TK can be incrementally added by the user to bias the creation of any test. The TK can be linked to the data, length, or address of any resource, and it can influence the generation of any event. In such a way, the scope and sharpness of the Genesys test-programs are truly unlimited—they are determined by the investment made by its users. Depending on how it is defined in the specification model, TK can be taken into account during random generation (referred to as default TK) or only when specifically requested (specific TK). Genesys relies on a formal and declarative model of the architecture captured separately in its architecture model component. This structure allows the convenient integration of architectural changes, which are very common during design development. More generally, it enables the adaptation of Genesys to a wide range of different architectures, with minimal effort. The latest trend of designing hybrid microprocessors (e.g., Merced, which mixes x86 with VLIW) emphasizes the importance of having a tool which is easily customized to any architecture. Contrary to typical test cases, which assume initiation from the reset state of the design, Genesys allows a test to start from any (legal) state. It enables the user to bring the design directly into a state that otherwise would have been relatively hard to reach. The sole output of the generator is a test file which consists of a sequence of instructions starting from a given initial state, and a section of expected results describing the expected values of the various processor resources. Both properties, initial state and expected results, contribute to the production of short, easy-to-debug and incisive tests. Instruction Control Genesys is primarily an instruction-driven test generator. This means the entire test generation is based upon the selection of the instructions that will appear in the test. The generation scheme is such that Genesys first selects an instruction and only then attempts to fulfil the existing biasing requests (i.e., the generation of some event). The instruction selection is controlled by the following biasing directives: Instruction selection: There are several options for selecting from the available instructions: each one separately, as a set (either predefined in the database or built by the user), as a format, or using a macro (which is a user-defined sequence of instructions). Another option is enumeration over a set of instructions, which is a feature that is especially useful for coverage purposes. Policy order: The relative ordering of the instructions may be random, ordered, or cyclic. Control over the instructions that will appear in the not-taken leg of a branch instruction. Loops: Specific control is provided in order to control the generation of loops. Resource Control Genesys offers control over resources, such as registers and memory locations, which will participate as input and output of the instructions. It is important to note that control is given in two distinct scopes—global and specific (per instruction). In all the biasing directives, varying degrees of randomness are allowed. For example, in address selection, the level of biasing may vary from high-level specification, such as stipulating the degree of alignment, boundary, and crossing relative to any standard storage size (i.e., word or page). At the other extreme of low-level biasing, one may control specific bits of the address. The list below summarises the different controls provided: Resource initialization: The user may initialize any resource defined by the architecture (registers, memory, initial address). During test generation, resource reloading is also supported. Resource selection policy: Addresses and registers can be selected according to multiple policies, differing mainly in their relative reuse of the resources. Field biasing: The content and occurrence of the instruction fields are under complete user control. Address biasing: The user has comprehensive control over the addresses that will be accessed during the test. This includes both the effective addresses and physical memory. Genesys supports address translation, allowing the user extended control on the generation of all possible events that may occur during translation. This includes events such as aliasing and all types of exceptions. The provided support is, of course, design dependent, because address translation mechanisms may differ greatly between architectures. Cache usage biasing: Genesys provides biasing directives toward all the main cache events (Hit, Miss, Replace, Transfer-in, Transfer-out) using a simple cache model, where addresses reach the cache in the order in which they appear in the instruction stream. Genesys supports multiple caches for both data and instructions, including hierarchical relationships between them. They are defined through the knowledge base, along with their particular parameters. Symbols: Symbols can be specified instead of any resource, providing a means for conveniently creating dependencies between resources, without having to specify their exact identity.