No, Genesys can support different architectures, even complicated structures such as the x86 architecture.

Genesys tests aren't run-able on real hardware directly, but after conversion they can be run on real hardware. The main issue that the converter should handle is the initialization of the machine resources.

Depending on the specific architecture, it usually takes a few months.

Usually customers supply their own reference models and use a simple interface to Genesys.

Although, as a rule, Genesys avoids reaching occupied addresses, it does allow the generation of controlled loops.

Yes, Genesys uses a supplied interrupt handler and continues with the generation.

No, Genesys is limited by the architectural simulator, which cannot simulate external interrupts. However, using several assumptions, it is possible to check this in a limited way.

Yes, Genesys supports cache verification to some extent. It doesn't know the exact status of the cache, but it does keep a simple model of the cache. Through this model, Genesys can generate cache events on a probability basis.

Yes, Genesys generates the address translation path for all the memory accesses (when the address translation switch is on). It even gives the user full biasing control of the different events that are connected to the process, including interrupts and aliasing.

Genesys uses the simulator to define how those situations are defined in a specific design. Situations that are not defined, even in the specific design, are not generated, or Genesys re-initiates the undefined resource before its next use.

There is a multiprocessor test program generator version of Genesys, named Genie. Genie is designed for an architecture level verification of shared-memory multiprocessors. The output of the tool is a concurrent program and the predicted state of the shared-memory and the processor resources (registers) at the end of the program's execution.