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Floating-Point Test Generator - FPgen

Processor Verification Technologies

Publications

  • "Simulation Based Verification of Floating Point Division", to appear in IEEE Transactions on Computers, 2010.
    available in (pdf, 231 KB)
  • "Implementation Specific Verification of Divide and Square Root Instructions", in Proc Arith19, 2009, pp.114 - 124.
    available in (pdf, 547 KB)
  • "Decimal floating-point in z9: an implementation and testing perspective", IBM Journal of Research and Development, Volume 51, Number 1/2, 2007, pp. 217 - 228.
    available in (pdf, 172 KB)
  • "Solving Constraints on the Intermediate Result of Decimal Floating Point Operations", To appear in Proc. Arith 18, 2007.
    available in (pdf, 142 KB)
  • "Solving Constraints on the Invisible Bits of the Intermediate Result for Floating-Point Verification", In Proc. Arith17, 2005, pp. 76 - 83.
    available in (pdf, 79 KB)
  • "FPgen - A Test Generation Framework for Datapath Floating-Point Verification". In Proc. IEEE International High Level Design Validation and Test Workshop 2003 (HLDVT03), 2003.
    available in (pdf, 203 KB)
  • "Solving Range Constraints for Binary Floating-Point Instructions", In proc. ARITH16, 2003, pp 158-164,
    available in (ps, 174 KB , pdf, 78 KB)
  • "Test Generation for the Binary Floating-Point Add Operation With Mask-Mask-Mask Constraints", Theoretical Computer Science, Vol. 291/2 (2002) pages 183-201,
    available in (ps 250 KB , pdf 222 KB)