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FoCs

Formal Verification


Bridge to VCS


Users of the Synopsys VCS simulator can very easily use PSL/Sugar, thereby leveraging the language in multi-vendor design flows. Specifically, to develop VCS based testbenches that involve PSL/Sugar assertions, one uses the FoCs tool to convert the PSL/Sugar assertions into Verilog or VHDL checking modules that are conjoined with the simulated design. Click here for specific instructions. In a recent interview, a marketing director in Synopsys has referred to this way of translating PSL/Sugar into Verilog:

"There are ways to convert Sugar into Verilog. There is a tool called FoCs (from IBM) that will do it and we see that as a way to use those properties"

Swami Venkat, Director of Marketing for Testbench and Formal Verification tools in Synopsys
IEE Embedded and Real Time Systems Industry News 2003-07-31
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Click to see full IEE article

Synopsys is a registered trademark of Synopsys, Inc. VCS is a trademark of Synopsys, Inc.

 
 

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