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FoCs

Formal Verification


Overview


FoCs (pronounce 'fox') takes Sugar properties (a.k.a. assertions) and translates them into HDL Checkers, which in turn are integrated into the simulation environment. These Checkers monitor the simulation results on a cycle-by-cycle basis for violation of the properties. Each Checker implements a state machine that enters and asserts an error state if the respective property fails to hold in a simulation run.

Users of FoCs report a drastic improvement - up to 50% - in testbench development time.



 
Contact
Sivan Rabinovich
IBM Haifa Research Laboratory
Haifa University Campus
Mount Carmel
Haifa 31905
ISRAEL
email : sivanr@il.ibm.com
 

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