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With the increasing complexity of processor designs, the number of functional bugs grows beyond the capability of verification to handle. We seek to improve the logic design process to reduce the number of functional bugs in the design.

One of the challenges logic designers face is that of timing closure, i.e., making fixes in their RTL based on synthesis feedback to enable the design to run in the required frequency.

We are developing Tiger (Timing Debugger), a tool that assists the physical and logic designers by bringing together timing information from all sources and by portraying it in a convenient and graphical manner.