With the advancement of digital processing capabilities, replacement of traditional analog chip components with digital circuits is becoming an important design direction in complex analog systems such as beam forming phase-shifters, serial links, and base-band signal processing. Digital realization enables a flexible system configuration and easy reuse of the developed IP. The fast, low power, analog-to-digital converter (ADC) front-end is a technology enabler for transferring analog signals into the digital domain. To compete with analog circuit solutions, the power consumption of the ADC must be reduced to ultra low levels, below or equivalent to those of the original analog circuits. Reducing the power of the ADC is therefore the main challenge in modern ADC design.
The group is involved in developing a fast (x Gsps) medium resolution (6-7 bit) low power ADC. Power reduction is achieved using efficient circuit architecture, minimum device dimensions, and extensive digital calibration schemes.