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IBM Research

RuleBase Parallel Edition

Formal Verification

Generalized Buffer (PSL/Sugar version)

Using the VHDL files

  • In the second screen, you are asked to provide a name for the tutorial project. We suggest using the name "GENBUF".

  • In the third screen, you are asked about the top-level environment and rules file. Our 'school solution' recommendation is to use the envs file (under the genbuf directory). In the next sections of this tutorial, you can find instructions on making your own envs file. Make sure that the "PSL GDL Flavor" option in the "Specification Language" is selected and the PSL version is set to IEEE.

  • In the fourth screen, you are required to select the design type file that describes the GENBUF block. As explained, only the Portals compiler is suitable for this design, so choose the "Portals VHDL Compiler" option in the combo box.

  • In the fifth screen, you must specify where the VHDL files can be found. In the "Makefile" value field, you are required to specify the makefile file (found in the genbuf directory) that contains all the names of the necessary VHDL files. In the "Entity" value field, write the name: GENBUF.
    In addition, you should specify two VHDL libraries: "ieee" and "ibm" (in that order), which are necessary for making the compilation.
    To add the libraries, just click on the "VHDLPATH" value field. A button with an ellipsis (...) is displayed. Click that button, and a new window opens. Click Add.
    The vhdllibs directory that resides in your RuleBase/PE install directory contains these two sub-directories. First choose the path for the "ieee" directory and afterwards choose the "ibm" path (the order is important).

  • Skip the sixth screen and click Finish in the final screen.

After selecting Finish, the Project Configuration Wizard closes, and the RuleBase/PE GUI main screen is displayed, with all the available features.

To perform the compilation, click File -> Compile Design.


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