As it becomes necessary to provide a technique for easy design exploration and verification on a block level, before the complicated formal/simulation environment is ready, there's a need for an easy, interactive tool that allows a quick entry into the design exploration. Diver is a graphical tool intended for designer-level verification. It provides designers with an easy interface for simulating their RTL under selected prime scenarios. The simulation process includes specifying input stimuli patterns, clicking the Simulate button, and analyzing the results appearing as a timing diagram.
Diver is being used intensively by IBM logic designers to verify they own RTL. It has been proven to be an easy-to-use tool which provides great flexibility in supporting various designer-level verification tasks.
Diver Main Window
Working with Diver
Diver is built on the concept of scenarios. A scenario in Diver is a graphical, timing-diagram like, description of a desired behavior of the design. A scenario can include random behaviour of primary inputs, overriding values on internal signals and expected results on internal or output signals. Diver goes beyond simulating just input patterns. It also allows designers to specify scenarios in terms of internal events or output events, and then find the input patterns that can make these events happen. For that purpose, Diver interfaces with a formal analysis tool. Having such a tool under the hood will also allow designers to go as far as assertion-based verification.
Diver can work with designs written in VHDL, Verilog and SystemVerilog, and can handle embedded SVA and PSL assertions. Diver provides its own wave-viewer for examining simulation results. In addition it can integrate with an external wave-viewer supporting the VCD file format.
Diver supports several use-cases common to designer-level verification. With Diver logic designers can easily:
- Explore new designs by creating simple scenarios for showing mainstream behaviors.
- Explore corner-case behaviors of their designs.
- Check whether existing assertions and coverage events can be hit.
- Perform bug-hunting using random behavior and expected result specification.
Diver can also be used to import a waveform file generated by simulation and project it onto the current block for further examination and debug, using what-if analysis.
Diver is avaialable for use outside of IBM through a licensing process governed by IBM Research. Please contact Eli Arbel for more details on licensing.