The PROSYD EU initiative led by IBM Research delivers a 50% quality gain and almost 20% reduction in development time
Haifa, Israel June 2007 - The IBM-led European Union collaborative research effort has succeeded in dramatically improving the productivity of chip design methodology. PROSYD was a three-year, €7M project centered around the recently standardized IEEE 1850-2005 Property Specification Language (PSL). The aim of PROSYD was to streamline the chip design process by creating a reference methodology and an associated toolset based on PSL, which promotes the reuse of design specifications -- in the form of properties -- across the specification, design, and verification phases.
"This new property-based paradigm will streamline the chip design process and enable the development of higher quality electronic systems within shorter design cycles and with lower costs," noted Cindy Eisner, Senior Architect for Verification Technologies at the IBM Haifa Research Lab and coordinator of PROSYD.
More specifically, the PROSYD project brought to life the new Property Visualization feature of the RuleBase model checker. RuleBase is the world renowned industrial-strength formal verification (FV) tool developed at the IBM Haifa Research Lab. The new Property Visualization feature, based on the Property Assurance and Simulation tool developed by PROSYD academic partners ITC-IRST and TU Graz, allows engineers to develop and debug property-based specifications at the start of the design process, rather than waiting until the verification phase towards the end of the design cycle.
The PROSYD partners represented a wide range of expertise in system design and verification, and in particular have collaborated in the standardization of PSL. The project was initiated by researchers from the IBM Haifa Research Lab in Israel and gathered the talents of leading European systems companies, R&D centers, and universities, including Infineon Technologies, STMicroelectronics, OneSpin Solutions, the Technical University of Graz, ITC-IRST, Verimag, and the Weizmann Institute of Science.
The PROSYD case studies, based on sixteen designs from Infineon, STMicroelectronics and IBM, clearly demonstrated that following the property-based methodology results in an impressive quality gain averaging 50%, as measured by the reduction in the number of bugs found during chip integration. Furthermore, there is no tradeoff between quality and productivity. On the contrary, the quality gain is accompanied by an improvement of 14-19% in development time across the design cycle.
More information about PROSYD can be found on the PROSYD home page at http://www.prosyd.org/.