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Solution for modeling interconnects in high speed multi-GHz chip designs

IBM Haifa Labs News Center


October 23, 2006


T-line technology from IBM Research Lab in Haifa helps designers design and model transmission lines in high speed circuits.


In high speed multi-GHz chip designs, interconnects are rapidly becoming a limiting factor in the performance, greatly influencing energy dissipation and signal integrity.

At high data rates, the demanding requirements for on-chip wiring pose a serious problem, from the aspects of both design flow and modeling. Previous attempts to tackle this problem in analog and mixed signal (AMS) designs and most other silicon chip technologies are based on the post-layout extraction approach. Unfortunately, this solution fails in the multi-GHz domain, because it cannot correctly evaluate the wire inductances, due to inability to determine the correct current return paths, not to mention other high frequency effects, such as skin-effect and distributed effects of long critical wires.

Back in 1998, a team led by researcher David Goren at IBM Haifa Research Labs developed a new approach, born as an attempt to resolve serious signal integrity issues in Silicon Germanium (SiGe) technology designs. At that time, there were no tools available to describe the on-chip wiring inductance or take it into account during the design process.

Since inductance related effects are important only for a relatively small number of critical wires in a given design, Goren team's approach identifies these lines in the pre-layout design stages. The critical wires are then designed using a unique set of transmission line templates, referred to as "on-chip T-lines" which are designed as "closed environment structures" with well-confined electric and magnetic fields. For each signal line, current return path designed as an integral part of the T-line device. The team introduced a small set of on-chip T-lines geometries that cover most design situations, and developed original semi-analytical models to predict their full frequency-dependent behavior from DC up to the cut-off frequency of the transistors in the given technology (skin and proximity effects, silicon substrate effects, crossing lines impact, etc.). An extensive set of measurements was performed on a comprehensively large number of test sites containing the on-chip T-lines, and proved to be accurate in predicting performance over the whole range of frequencies from DC up to 110GHz.

The T-line design flow for on-chip interconnect
Ever since 2000, the Haifa T-line models are an integral part of the IBM foundry Design Kits, first in SiGe technologies and gradually in all CMOS technologies, making it easy for designers both inside and outside IBM to gain quick and accurate interconnect characterization, without going into complex simulations and calculations.

The IBM Research team working on T-lines has since published 12 papers and filed 10 patents, with more on the way.

Eliminating the need for lengthy numerical solution of Maxwell's equations, the T-line models provide an elegant solution to a defined problem that combines physics, math, and engineering. The on-chip T-lines give IBM enhanced marketing differentiation due to the robustness, ease-of-use, and extendibility that they offer for every new technology generation.

 
 

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