System Verification Technologies
The demand for high performance hardware systems with limited power consumption is increasing the complexity of their design and architecture. Modern architectures are heterogeneous by nature and include many cores, general purpose and special purpose processors, accelerators, and complex IO adapters and interconnects. This ever-increasing complexity imposes an extremely difficult challenge on verification, which consumes up to 70% of the design effort.
In an attempt to provide best-of-breed solutions to this area, the System Verification Technologies group focuses on finding effective ways to verify the design of full systems. Our technology and tools support simulation-based verification of a large variety of system designs, ranging from gaming consoles (MS X-Box, Sony PS/3, and Wii) to very large, high-end, computer systems used by enterprises such as pSeries (the leading UNIX server) and zSeries (the leading mainframe computer). From a verification discipline perspective, we deal with two main challenges: reaching the bugs and exposing them.
Our main technology in the domain of reaching the bugs is X-Gen, a constrained-random stimuli generator for system verification. X-Gen supports a rich test-template language for describing system-level scenarios. Through this language, users may direct the tool to generate scenarios that range from specific to completely random, guided by encapsulated testing knowledge. X-Gen employs AI techniques-such as knowledge representation and constraint satisfaction problems-to tackle the challenge of system-level test generation. X-Gen provides a GUI for editing test-template files and a powerful modeling platform that allows easy introduction of new interactions and components to the system.
With respect to exposing the bugs, we work on future directions of the CML (Coherence Monitor Lite) technology. CML, which was developed at the Austin development center, is a framework designed to detect bugs that typically arise from the interaction of components in a complex SMP or a clustered system. CML was originally designed for simulation environments. We are currently working on scaling it to acceleration platforms due to their increasing significance in the verification process. In addition, we are exploring different alternatives for checking on acceleration platforms.
We're also exploring the hardware debugging domain. Debugging is an essential part of both the development and the verification process. As hardware systems become more complex, debugging is more challenging than ever. In this field we work on a trace-based visualization tool.
All of our technologies are developed in close cooperation with verification teams in different IBM sites (Austin, Rochester, Raleigh, Boeblingen, Bangalore).