Processor Verification Technologies
Simulation of automatically-generated test programs is the main means for verifying complex hardware designs. The Processor Verification Technologies group specializes in automatic test program generation technologies for high-end designs, with a focus on verifying processors and Symmetric Multi-Processor (SMP) systems. Our technologies are recognized as the best in the field and are used throughout IBM's major hardware development labs and by external customers.
Genesys-Pro Test Program Generator
Genesys-Pro can be customized to all architectures and is already customized to support the ARM architecture. Genesys-Pro is an industry-leading state-of-the-art test program generator for processor and multi-processor functional verification. Leveraging experience of over two decades in test generator development, the tool has enabled the verification of IBM Power architecture and non-Power architecture designs. Genesys-Pro is also licensed by external companies for the functional verification of their designs.
Floating-Point Test Generator - FPgen
FPgen is a test generator targeted toward the verification of the floating point datapath. FPgen is a generic tool that targets architectures compliant with IEEE Standard 754-2008. However, it can also be used for architectures that deviate from the standard. FPgen includes a generic test plan (GTP) for floating point to help verification engineers in the process of FPU datapath verification. This GTP is based on the experience accumulated during the verification of several processors in IBM, along with a deep knowledge and understanding of algorithms and design for the floating point unit. The GTP contains many interesting cases to be checked in simulation. It is coverage-oriented and comprises several coverage models, each targeting a specific part of the FPU, or a particular feature of floating point. These models are also implemented as input files for FPgen, giving the user a large base with which to begin the verification process.
Test Plan Automation
The Test Plan Automation (TPA) project explores new directions in processor-level test generation. We have defined two long term goals. The first goal is to develop a processor-level scenario definition language and supporting tools which enable a more efficient and higher quality implementation of directed test plans. The second goal is to define and implement an extendible generic test plan customizable for any architecture and micro-architecture. These goals are achieved by introducing an additional layer to the GenesysPro test generator. TPA raises the level of abstraction of the test-template language and brings it closer to the verification plan while relying on a microarchitectural model to provide specific details on microarchitecture behavior. In addition, TPA closes the gap between the test template and the generated test cases using new stream-solving generation algorithms and scenario-level testing knowledge.
The goal of the Verification Cockpit project is to create a central planning, tracking, analysis and control platform for large scale hardware verification projects. Based on the Rational lifecycle management and reporting tool set (including Rational Team Concert and Rational Insight), the project integrates existing standalone verification tools and data sources such as test plans, coverage, and test execution environments to a consolidated verification platform.
Our primary goal is to provide a constraint satisfaction solver as a core technology for the functional verification tools in our area. Beyond verification, we use our expertise and solving capabilities to solve complex constraint satisfaction problems in other areas, such as design floorplanning, pipeline scheduling, workforce management, truck configuration, and more.