Program Day 1 - Tuesday 15/11/2016

08:30 - 09:30 Registration and Welcome

09:30 - 09:45 Opening Remarks

09:45 - 10:45 Keynote: Current Trends and Future Direction in Eco-system of Hardware Formal Verification: A Technical and Business Perspective
Dr. Rajeev K. Ranjan, Senior Group Director, R&D Formal and Automated verification, Cadence
Session chair: Moshe Levinger

10:45 - 11:45 Technical Session: Hardware Verification
Session Chair: Hari Mony

SAT-based Combinational and Sequential Dependency Computation,
Mathias Soeken, Pascal Raiola, Baruch Sterin, Bernd Becker, Giovanni De Micheli and Matthias Sauer

Multi-core SCC-based LTL Model Checking,
Vincent Bloemen and Jaco van de Pol

11:45 - 12:15 Coffee Break

12:15 - 13:15 Technical Session: Hardware & Network Verification
Session chair: Ofer Strichman

Gating Aware Error injection,
Eli Arbel, Barak Erez, Bodo Hoppe, Udo Krautz, Shlomit Koyfman and Shiri Moran

ddNF: An Efficient Data Structure for Header Spaces,
Nikolaj Bjorner, Garvit Juniwal, Sanjit A. Seshia, George Varghese and Ratul Mahajan

13:15 - 14:30 Lunch

14:30 - 15:30 Keynote: Guiding Formal Methods with Discovered Knowledge
Prof. Swarat Chaudhuri, Rice University
Session chair: Karen Yorav

15:30 - 16:00 Coffee Break

16:00 - 17:30 Special session: Autonomous Systems, verification and design challenges
Session chair: Laurent Fournier

Verification of Intelligent Autonomous Systems: Some progress, many challenges,
Yoav Hollander, Founder, Foretellix ltd

Robust learning & planning under uncertainty, a crucial nail; formal verification, a nice hammer!,
Dr. Shashank Pathak, Autonomous Navigation and Perception Lab, Faculty of Aerospace Engineering, Technion

17:30 - 18:30 Reception and Posters

Keynote Speakers


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