Accepted Papers

  • Jakub Daniel and Pavel Parizek,
    PANDA: Simultaneous Predicate Abstraction and Concrete Execution
  • Heike Wehrheim and Oleg Travkin,
    TSO to SC via symbolic execution
  • Balázs Kiss, Nikolai Kosmatov, Dillon Pariente and Armand Puccetti,
    Combining Static and Dynamic Analyses for Vulnerability Detection: Illustration on Heartbleed
  • Jan Lanik and Oded Maler,
    On switching aware synthesis for combinational circuits
  • Jia Liang, Vijay Ganesh, Ed Zulkoski, Atulan Zaman and Krzysztof Czarnecki,
    Understanding VSIDS Branching Heuristics in Conflict-Driven Clause-Learning SAT Solvers
  • Martin Leucker, Grigory Markin and Martin R. Neuhäußer,
    A new Refinement Strategy for CEGAR-based Industrial Model Checking
  • Raviv Gal, Avi Ziv, Michael Behm, Klaus-Dieter Schubert, John Reysa, Gil Shurek, Moab Arar, Einat Kermany, Alex Goldin, Bilal Saleh, Odellia Boni and Maxim Ilyaev,
    The Verifiation Cockpit - Creating the Dream Playground for Data Analytics over the Verification Process
  • Jin Hyun Kim, Brian Nielsen, Kim G. Larsen, Marius Mikucionis and Axel Legay,
    Resource-Parameterized Timing Analysis of Real-Time Systems
  • Sergiy Bogomolov, Christian Schilling, Ezio Bartocci, Gregory Batt, Hui Kong and Radu Grosu,
    Abstraction-based Parameter Synthesis for Multiaffine Systems
  • Dejanira Araiza-Illan, David Western, Anthony Pipe and Kerstin Eder,
    Coverage-Driven Verification - An approach to verify code for robots that directly interact with humans
  • Lenore Zuck and Sanjiva Prasad,
    Limited Mobility, Eventual Stability
  • Rajarshi Ray, Amit Gurung, Binayak Das, Ezio Bartocci, Sergiy Bogomolov and Radu Grosu,
    XSpeed: Accelerating Reachability Analysis on MultiCore Processors
  • Jianwen Li, Shufang Zhu, Geguang Pu and Moshe Vardi,
    SAT-Based Explicit LTL Reasoning
  • Andrew Becker, Djordje Maksimovic, David Novo, Mohsen Ewaida, Andreas Veneris, Barbara Jobstmann and Paolo Ienne,
    FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction
  • Martin Nowack, Katja Tietze and Christof Fetzer,
    Parallel Symbolic Execution: Merging In-Flight Requests
  • Christian Herrera, Bernd Westphal and Andreas Podelski,
    Quasi-equal Clock Reduction: Eliminating Assumptions on Networks
  • Ping Yeung,
    Multi-Domain Verification of Power, Clock and Reset Domains

Keynote Speakers

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