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Verification Seminar 2003

Visitors information
Confirmed participants
Verification in HRL

Seminar's Agenda (pdf 80KB)

9:15 Arrival

9:30 Welcome,
Michael Rodeh, Director, IBM Haifa Labs

9:45 Predictable Design by Pre-Implementation Validation of Non-functional Properties,
Wolfgang H. Nebel, Oldenburg University, OFFIS and ChipVision Design Systems (Abstract)

10:25 Deep Knowledge Test Generators and Functional Verification Methodology,
Laurent Fournier, IBM Haifa Labs (Abstract , Presentation)

10.55 Stochastic Approach to Constraint Satisfaction Problems in the Hardware Verification Domain,
Yehuda Naveh , IBM Haifa Labs (Abstract , Presentation)

11:25 Coffee break

11:40 MSIL DSP Platform Verification Methodology,
Amit Gur, Verification Leader of DSP platform, Motorola (Abstract , Presentation)

12:10 Formal Verification or Simulation: Why not both?
Michel Jalfon, Analog Devices (Abstract , Presentation)

12:40 Lunch

13:50 Keynote: A Survey of Abstraction Refinement Techniques,
Fabio Somenzi, University of Colorado at Boulder (Abstract)

14:40 An Optimized Symbolic Bounded Model Checking Engine,
Rachel Tzoref, IBM Haifa Labs (Abstract , Presentation)

15:10 Reasoning About Truncated Paths,
Dana Fisman, Weizmann Institute of Science (Abstract)

15:40 Break

16:00 High End Router Line Card Verification,
Rami Zemach, Routing Technology Group, Cisco System Israel (Abstract)

16:30 Coverage Oriented Verification of Banias,
Alon Gluska, Intel, Haifa (Abstract , Presentation)

17:00 Concluding Remarks,
David Bernstein, Mgr., Software and Verification Technologies, IBM Haifa Labs

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